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authorMatt DeVillier <matt.devillier@gmail.com>2023-10-21 20:38:01 -0500
committerFelix Held <felix-coreboot@felixheld.de>2023-10-23 20:59:36 +0000
commitea2a47667e88cc68399381f9ec640cd9d74a6b25 (patch)
tree59c04720e20cda027d6fa5d8e2cb63d5d2dd230d /src/soc/intel
parent06fe0d7828a6529b22b88ca0f610a918f2589e39 (diff)
soc/intel/tigerlake: Add ACPI devices for FSPI, SRAM, HEC1
Add ACPI devices for these components so that generated LPI constraints for them have valid device references. TEST=tested with rest of patch train Change-Id: Ib70dc29f54d28ec1fe7b630ab3fab24bcdd08154 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78519 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/tigerlake/acpi/pcie.asl10
-rw-r--r--src/soc/intel/tigerlake/acpi/serialio.asl6
2 files changed, 16 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/acpi/pcie.asl b/src/soc/intel/tigerlake/acpi/pcie.asl
index 9c98dde129..a25335cb91 100644
--- a/src/soc/intel/tigerlake/acpi/pcie.asl
+++ b/src/soc/intel/tigerlake/acpi/pcie.asl
@@ -475,3 +475,13 @@ Device (RP24)
}
}
#endif /* CONFIG(SOC_INTEL_TIGERLAKE_PCH_H) */
+
+Device (SRAM)
+{
+ Name (_ADR, 0x00140002)
+}
+
+Device (HEC1)
+{
+ Name (_ADR, 0x00160000)
+}
diff --git a/src/soc/intel/tigerlake/acpi/serialio.asl b/src/soc/intel/tigerlake/acpi/serialio.asl
index f7bf452058..5314db0418 100644
--- a/src/soc/intel/tigerlake/acpi/serialio.asl
+++ b/src/soc/intel/tigerlake/acpi/serialio.asl
@@ -79,3 +79,9 @@ Device (UAR2)
Name (_ADR, 0x00190002)
Name (_DDN, "Serial IO UART Controller 2")
}
+
+Device (FSPI)
+{
+ Name (_ADR, 0x001f0005)
+ Name (_DDN, "Fast SPI")
+}