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2023-03-21soc/intel/apl: Fix programming temporary MTRR on GLKArthur Heymans
Programming MTRR happens later in the CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT codepath. fast_spi_cache_bios_region() assumes an existing MTRR solution from x86_setup_mtrrs_with_detect(). This fixes a problem introduced by 829e8e6 "soc/intel: Use common codeflow for MP init". Change-Id: I9b6130cf76317440ebe7a7a53e460e2b658d198e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73836 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-21soc/intel/common/block/acpi: Support more than 255 coresPatrick Rudolph
Replace the legacy ACPI Processor() object as it only supports 8bit IDs and thus no more than 255 cores. Use the new ACPI Device() object that supports more than 255 cores. Test: - Observed no ACPI errors on IBM/SBP1 and Linux 5.15 running 384 CPU cores in total. - Verified on Intel ADL RVP with 20 cores that Linux 5.15 is still working without errors. Change-Id: I309c06b6824704c84fd16534655334a6f269904a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73578 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-03-21soc/intel/elkhartlake: Make PCIe root port speed limit configurableMario Scheithauer
In cases where there are limitations on the connected device behind the PCIe root port it can be necessary to limit the speed. The FSP parameter 'PcieRpPcieSpeed' allows to set the speed limit. This patch provides a chip config so that this FSP parameter can be set as needed in the devicetree on mainboard level. Change-Id: I9fc24de1682279e4ae4c090147a6ef7995b441bc Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-03-21soc/intel/alderlake/vr_config: Add i3-1220PEPatrick Rudolph
Add the AlderLake-P 4+4+2 (28W) with MCH_ID 0x4629 to the vr_config table. Change-Id: I606ef429f47dfe386177f7257b153acc1611bb61 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-03-20soc/intel/meteorlake: Enable GPIO IOSTANDBY configurationSubrata Banik
Enable SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY so the pads can be configured with non-zero IOSSTATE values. TEST=Able to build and boot google/rex. GPIO debug print is showing GPIO PAD config DW1 bit[14:17] are getting programmed. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9e63fe946d541769fa0ddbb23f902f9c905735c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-19soc/intel/xeon_sp/Makefile.inc: Build EBG for SPR-SPTim Chu
Intel SPR-SP chipset has EBG instead of LBG. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: I9429fe332bb5f01a41aa205c76ad9f0159f93eee Reviewed-on: https://review.coreboot.org/c/coreboot/+/71959 Reviewed-by: Jian-Ming Wang <jianmingW@supermicro.com> Reviewed-by: TimLiu-SMCI <timliu@supermicro.com.tw> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-19soc/intel/xeon_sp/spr: Add Sapphire Rapids ramstage codeJonathan Zhang
It implements SPR ramstage including silicon initialization, MSR programming, MP init and certain registers locking before booting to payload. Change-Id: I128fdc6e58c49fb5abf911d6ffa91e7411f6d1e2 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-19soc/intel/xeon_sp/spr: Add header files and romstage codeJonathan Zhang
Several FSP HOBs processing codes are similar to Intel Cooperlake-SP codes in soc/intel/xeon_sp/cpx. Register datasheet please reference Sapphire Rapids EDS Vol2 Doc#612246 and Emmitsburg PCH EDS Doc#606161. Change-Id: Ia022534e5206dbeec946d3e5f3c66bcb5628748f Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-19soc/intel/mtl: Choose serial msg `log_level` based on DIMM countSubrata Banik
This patch modifies the serial msg log_level at runtime to highlight an ERROR if the DIMM count is zero. It would help to draw the attention while parsing the serial msg and catch any underlying issue. TEST=Able to see ERROR msg while booting google/rex with FSP v3064 Without this patch: [DEBUG] 0 DIMMs found With this patch:     [ERROR]  No DIMMs found Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iacf41efecb4962f91cf322bbc50636dc44033e3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/73756 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-19soc/intel/xeon_sp: add MSR definitions for SPR-SPDavid Hendricks
Some MSRs used in SPR code are common among currently supported Xeon-SP generations and are added to the top-level Xeon-SP msr.h. MSRs which have changed are added to SPR's soc_msr.h. Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: David Hendricks <ddaveh@amazon.com> Change-Id: I92b433a9686734716dc7936895fb79c7751f7f9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/73172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-03-19soc/intel/xeon_sp: Split SKX/CPX MSRs into separate headersJonathan Zhang
Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: David Hendricks <ddaveh@amazon.com> Change-Id: I2ecfebdde453a48b7b0e6f21b3c4394411eed671 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-03-19soc/intel/xeon_sp: Add P2SB definition for SPR-SPJonathan Zhang
Change-Id: I2ece7aac4339266068d4fc8fb1c58d0573eb2895 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Simon Chou <simonchou@supermicro.com.tw> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-03-17soc/intel/alderlake: Hook the VT-d DMA protection optionMichał Żygowski
TEST=Enable DMA protection on MSI PRO Z690-A DDR4 and observe the I/O devices like USB and NVMe fail to enumerate in UEFI Payload (basically proving that DMA protection works). Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Iecaa3d04f1447b7e73507ca57a0d23d42e24d663 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68450 Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-17soc/intel/alderlake/hsphy.c: Handle case with DMA protectionMichał Żygowski
The HSPHY firmware must be downloaded to DMA-allowed host address space. Check for DMA buffer presence and use it as the buffer for HSPHY firmware to be downloaded from CSME. TEST=Successfully load HSPHY firmware to CPU on MSI PRO Z690-A DDR4 with DMA protection enabled. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I88edda26a027b557eeaba80426a5b7be7199507d Reviewed-on: https://review.coreboot.org/c/coreboot/+/68556 Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-17soc/intel/alderlake: Select SOC_INTEL_COMMON_BLOCK_VTDMichał Żygowski
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I226305fa547e9d9ea541a5806d543aa358bce28d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72069 Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-17intelblocks/vtd: Add VT-d block with DMA protection APIMichał Żygowski
Add new common block with VT-d/IOMMU support. The patch adds an option to enable DMA protection with PMR. However the payload and OS must support VT-d in order to properly handle I/O devices. TEST=Enable DMA protection on MSI PRO Z690-A DDR4 and observe the I/O devices like USB and NVMe fail to enumerate in UEFI Payload (basically proving that DMA protection works). Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Id7edf982457c1139624e5cd383788eda41d6a948 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
2023-03-15soc/intel/xeon_sp: Rename nb_acpi.c to uncore_acpi.cJohnny Lin
With newer xeon_sp processors, the concept of "north bridge" became obsolete, instead uncore should be used. Therefore we use uncore_acpi.c (instead of nb_acpi.c) going forward. Change-Id: I91ec9023152996bf9f2300a369aff3c4f19d75fd Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-03-15soc/intel/tigerlake: Select `X86_CLFLUSH_CAR` configLean Sheng Tan
This patch selects `X86_CLFLUSH_CAR` config for running `clflush` to invalidate the cache region based on commit 3134a81 for boot performance improvement. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I97c8c07db9b44aa89b433e7962ec77c8501ecaa9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-15soc/intel/elkhartlake: Select `X86_CLFLUSH_CAR` configLean Sheng Tan
This patch selects `X86_CLFLUSH_CAR` config for running `clflush` to invalidate the cache region based on commit 3134a81 for boot performance improvement. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I8f8a0bfeaea508d3b4ad1b3fe2e68742cbab5570 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73687 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-15soc/intel/coffeelake: Select `X86_CLFLUSH_CAR` configLean Sheng Tan
This patch selects `X86_CLFLUSH_CAR` config for running `clflush` to invalidate the cache region based on commit 3134a81 for boot performance improvement. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Icd3d16ab2cb34dc81fc12ec139c52ecaa170528d Reviewed-on: https://review.coreboot.org/c/coreboot/+/73686 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-15soc/intel/alderlake: Select `X86_CLFLUSH_CAR` configLean Sheng Tan
This patch selects `X86_CLFLUSH_CAR` config for running `clflush` to invalidate the cache region based on commit 3134a81 for boot performance improvement. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I1fe6072a3c23a02c9a691406f179bfc8f0f18a93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-13soc/intel/meteorlake: Enable early caching of TOM regionSubrata Banik
Intel Meteor Lake decides to enable early caching of the TOM region to optimize the boot time by selecting `SOC_INTEL_COMMON_BASECODE_TOM` config. TEST=Able to build and boot google/rex to ChromeOS and reduce the boot time by 77 ms. Without this patch: 950:calling FspMemoryInit 936,811 (19,941) 951:returning from FspMemoryInit 1,041,935 (105,123) With this patch: 950:calling FspMemoryInit 905,108 (20,103) 951:returning from FspMemoryInit 964,038 (59,929) Change-Id: Iebb3485b052386b43d5bccd67a04e6115cbcc20d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73274 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-13soc/intel/cmn/sa: Store TOM into the CMOSSubrata Banik
This patch uses the IA common code API to store the top_of_ram (TOM) address intonon-volatile space (CMOS). The code logic will update the TOM address in CMOS NVS if the `top_of_ram` address is calculated differently in any boot and also takes care of caching the updated range. TEST=Able to build and boot google/rex to ChromeOS. First boot: Before calling into FSP-M [DEBUG]  0x00000000fef00006: PHYBASE0: Address = 0x00000000fef00000, WB [DEBUG]  0x00003ffffff80800: PHYMASK0: Length  = 0x0000000000080000, Valid [DEBUG]  0x00000000fef80006: PHYBASE1: Address = 0x00000000fef80000, WB [DEBUG]  0x00003ffffffc0800: PHYMASK1: Length  = 0x0000000000040000, Valid [DEBUG]  0x00000000ff000005: PHYBASE2: Address = 0x00000000ff000000, WP [DEBUG]  0x00003fffff000800: PHYMASK2: Length  = 0x0000000001000000, Valid [DEBUG]  0x00000000f9800005: PHYBASE3: Address = 0x00000000f9800000, WP [DEBUG]  0x00003fffff800800: PHYMASK3: Length  = 0x0000000000800000, Valid ... [DEBUG] tom_table invalid signature [DEBUG]  top_of_ram = 0x76000000 [DEBUG] Updated the TOM address into CMOS 0x76000000 On consecutive boot:Before calling into FSP-M: The TOM region is already cached. [DEBUG]  0x00000000fef00006: PHYBASE0: Address = 0x00000000fef00000, WB [DEBUG]  0x00003ffffff80800: PHYMASK0: Length  = 0x0000000000080000, Valid [DEBUG]  0x00000000fef80006: PHYBASE1: Address = 0x00000000fef80000, WB [DEBUG]  0x00003ffffffc0800: PHYMASK1: Length  = 0x0000000000040000, Valid [DEBUG]  0x00000000ff000005: PHYBASE2: Address = 0x00000000ff000000, WP [DEBUG]  0x00003fffff000800: PHYMASK2: Length  = 0x0000000001000000, Valid [DEBUG]  0x00000000f9800005: PHYBASE3: Address = 0x00000000f9800000, WP [DEBUG]  0x00003fffff800800: PHYMASK3: Length  = 0x0000000000800000, Valid [DEBUG]  0x0000000075000005: PHYBASE4: Address = 0x0000000075000000, WP [DEBUG]  0x00003fffff000800: PHYMASK4: Length  = 0x0000000001000000, Valid Change-Id: I2569495570652c488096f6a29f58dd8f0103af9d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73273 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-13soc/intel/cmn/tom: Cache TOM region earlySubrata Banik
This patch implements a module that can store the top_of_ram (TOM) address into non-volatile space (CMOS) during the first boot and use it across all consecutive boot. As top_of_ram address is not known until FSP-M has exited, it results into lacking of MTRR programming to cache the 16 MB TOM, hence accessing that range during FSP-M and/or late romstage causing long access times. Purpose of this driver code is to cache the TOM (with a fixed size of 16MB) for all consecutive boots even before calling into the FSP. Otherwise, this range remains un-cached until postcar boot stage updates the MTRR programming. FSP-M and late romstage uses this uncached TOM range for various purposes (like relocating services between SPI mapped cached memory to DRAM based uncache memory) hence having the ability to cache this range beforehand would help to optimize the boot time (more than 50ms as applicable). TEST=Able to build and boot google/rex to ChromeOS. Without this patch: 950:calling FspMemoryInit               936,811 (19,941)   951:returning from FspMemoryInit        1,041,935 (105,123) With this patch:  950:calling FspMemoryInit               905,108 (20,103)   951:returning from FspMemoryInit        987,038 (81,929) Change-Id: I29d3e1df91c6057280bdf7fb6a4a356db31a408f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73272 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-13soc/intel/meteorlake: Select `X86_CLFLUSH_CAR` configSubrata Banik
This patch selects `X86_CLFLUSH_CAR` config for running `clflush` to invalidate the cache region. TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6b2dce39f82e28cd99ad8621c78bae494c4f16ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/73333 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-10xeon_sp: Setup x2apic in SRATNaresh Solanki
Set up SRAT table in X2APIC mode when necessary. Change-Id: Ib8b4cebefe81f7b5514524dba2fa364eee4bb157 Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-09soc/intel/xeon_sp: rework lock_pam0123() to accomodate hidden SAD deviceJonathan Zhang
For Intel SPR-SP, the SAD device is hidden, so pcidev_path_on_bus() returns NULL. Therefore use pci_s_write_config32() instead. Move lock_pam0123() from finalize.c to util.c, to be together with unlock_pam_regions(). Change-Id: Ib08d423d8c4d482612077b66dab3878018da8f2b Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-03-09soc/intel/xeon_sp: use get_socket_ubox_busno() to hide soc specificsJonathan Zhang
Intel SPR-SP has its specific way to get the bus number of ubox. Move the current implementations to CPX-SP and SKX-SP folders. Change-Id: I2b69be74d140115f9f78bc991fb690e3c90c88db Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-03-09soc/intel/broadwell/gma: don't unconditionally remap all GPU PCI IDsFelix Held
This fixes the case where a Broadwell CPU is combined with an AMD or NVIDIA GPU would result in using the Broadwell GPU VBIOS file from CBFS for the discrete GPU too. A further improvement would be to use a list of the Intel iGPU PCI IDs like it is done in the Skylake code. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3eb50cb9a0539255d50e5cd8163f10c3a062cc4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/73611 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-03-09soc/intel: Update API name `pmc_send_bios_reset_pci_enum_done`Subrata Banik
This patch updates PMC API name from `pmc_send_pci_enum_done` to `pmc_send_bios_reset_pci_enum_done` to inform PMC IPC about BIOS done is also set along with PMC enumeration being done. BUG=b:270942083 TEST=Able to build and boot google/rex. Change-Id: I1cf8cb1ecadeb68c109be6b0e751a3f2c448ae4f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-03-07soc/intel/xeon_sp: Add PM definition for SPR-SPDavid Hendricks
Change-Id: I13ed156a1b967e87fa30b1867feed03c3d17b992 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: David Hendricks <ddaveh@amazon.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-03-07soc/intel/adl: Increase MAX_CPUS to 32 for RPLTim Crawford
Raptor Lake i9 CPUs have 8P+16E cores for a total of 32 threads. Change-Id: I26a729a585e7dc14f38c9092056eb0280726f053 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73514 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-05soc/intel/alderlake: Hook up ucode for RPL-P/H/UTim Crawford
Hook up microcode from 3rdparty repo for: - 06-ba-02 (CPUID signature: 0xb06a2) Change-Id: Icb2fc9350ebc33ef150f1ab5df1006ed956478d6 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-03-04xeon/spr: Set ACPI CPU string for 12bitNaresh Solanki
On platforms with more than 255 cores the ACPI CPU string would overflow and generate duplicates. Fix that by changing the string to hex and use 3 digits. Test: Able to boot without ACPI errors on IBM/SBP1 which has 384 actives cores. Change-Id: I1887928da0c049c27e2ec129f49051b24048b33b Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-03-04soc/intel/alderlake: Allow channel 0 for memory-downTim Crawford
Fixes detection of the on-board RAM (Samsung K4AAG165WA-BCWE) on the System76 Lemur Pro 11 (lemp11). Change-Id: Ibe56c0f2b81d660303429cd2e21a7bb6cd433da5 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-03-04soc/intel/alderlake: Add UWES ASL into xhci.aslScott Chao
Align support for enable wake-on-usb attach/detach as was introduced in Cannon Lake in commit 811284125f0a ("soc/intel/cannonlake: Add UWES ASL into xhci.asl"). This adds the USB Wake Enable Setup (UWES) ASL blocks required to inform the OS about plug wake events bits being set in the PORTSCN register configured by devicetree. BUG=b:230398487 BRANCH=none TEST=Verify USB-A device could wake up Moli. Signed-off-by: Scott Chao <Scott_Chao@wistron.com> Change-Id: Icbc427a89413f5fe3a4a533135cc2c39349a9580 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73173 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-03soc/intel/xeon_sp: Fix CBMEM corruptionPatrick Rudolph
On the 4 socket IBM/SBP1 platform with 384 cores lots of space for ACPI tables is required. Bump MAX_ACPI_TABLE_SIZE_KB to 400 to fix CBMEM corruption. Change-Id: Ifbd79e84097231b41f900425a2e8750dce71a25a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki.2011@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-02soc/intel/alderlake: Hook up ucode for RPL-S/HX B0Tim Crawford
Hook up microcode from 3rdparty repo for: - 06-b7-01 (CPUID signature: 0xb0671) Verified microcode blob was in CBFS on Clevo PD50SNE (system76/serw13), which has an i9-13900HX. Change-Id: If91ff9233a5e1dd1db76edf33a76c55f5dddc9b4 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-03-01soc/intel/xeon_sp/spr: Select DISABLE_ACPI_HIBERNATE to remove S4 stateTim Chu
Server platform doesn't have S4 state so select DISABLE_ACPI_HIBERNATE to remove S4 state from available sleepstates. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: Ie5ddb1a98cd5bbd854b915c93694d1ebcb9bddd2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-03-01soc/intel/alderlake: Hook up PchHdaAudioLinkHdaEnable to devicetreeSean Rhodes
The comment that the PchHdaAudioLink UPDs only configure GPIOs is incorrect. Setting this GPIO to 1 or 0 will not change the HDA GPIO configuration; it will make the sound work when set to 1, or not work when set to 0. Remove the incorrect comment and make the UPD configurable from the devicetree. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I6f27f41a4a4b3844a65d45d36aba37c3af1050a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2023-03-01soc/intel/{tgl,adl}: Replace _S3 with D3COLD_SUPPORT symbolSean Rhodes
Replace the SOC_INTEL_TIGERLAKE_S3 and SOC_INTEL_ALDERLAKE_S3 with the D3COLD_SUPPORT symbol, as it allows for more granular control. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I07e8c84e5ad8f390bfbac017dd23736e7a6ced9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/73291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-28soc/intel/meteorlake: Hook up FSP hyper-threading setting to option APIEran Mitrani
Select `HAVE_HYPERTHREADING` and hook up the hyper-threading setting from the FSP to the option API so that related mainboards don't have to do that. Unless otherwise configured (e.g. the CMOS setting or overridden by the mainboard code), the value from the Kconfig setting `FSP_HYPERTHREADING` is used. Port of commit a182faeb88a0 ("soc/intel/alderlake: Hook up FSP hyper-threading setting to option API") Change-Id: I0b3e1a4049312c6b1ec950382c92274e0350001f Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-02-27soc/intel/elkhartlake/romstage/fsp_params.c: separate debug paramsMichał Żygowski
This commit separates setting FSP debug params from the rest of code and configures FSP serial port parameters. Other ports (0x3E8 and 0x2E8) are omitted since Elkhart Lake FSP only supports 0x3F8 and 0x2F8. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I84f7c19a7c2fd5a4db18f5a37e1c667da017aace Reviewed-on: https://review.coreboot.org/c/coreboot/+/72404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2023-02-27tree: Move 'asmlinkage' before type 'void'Elyes Haouas
Move 'asmlinkage' before the function type for consistency. Change-Id: I293590ef917b78c6ed3d151cd0080e42d0f10651 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73259 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-26soc/intel/xeon_sp: Drop unused cpu.h headerArthur Heymans
Change-Id: I42856424d3b55107f1758fb05f7ddbee3550d8b2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-02-25soc/intel/{adl, cmn, mtl}: Refactor MP Init related configsSubrata Banik
This patch optimizes CPU MP Init related configs being used within multiple SoC directory and moving essential configs into common code to let the SoC user to choose as per the requirement. TEST=Able to build and boot google/kano and google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I12adcc04e84244656a0d2dcf97607bd036320887 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-02-24soc/intel/ehl: Select CSE defined ME spec version for elkhartlakeDinesh Gehlot
Elkhartlake based SoCs uses Intel's Management Engine (ME), version 15. This patch selects ME 15 specification defined at common code and removes elkhartlake SoC specific ME code and data structures. BUG=b:260309647 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I3186f509c63b3a892c72cb1fa08fc094735d6eeb Reviewed-on: https://review.coreboot.org/c/coreboot/+/73245 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-24soc/intel/adl: Select CSE defined ME spec version for alderlakeDinesh Gehlot
Alderlake based SoCs uses Intel's Management Engine (ME), version 16. This patch selects ME 16 specification defined at common code and removes alderlake SoC specific ME code and data structures. BUG=b:260309647 Test=Build verified for brya. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ib94e4662c735b1c31c8dfca1cfa881e6fa4070fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/73244 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-24soc/intel/cnl: Select CSE defined ME spec version for cannonlakeDinesh Gehlot
Cannonlake based SoCs uses Intel's Management Engine (ME), version 12. This patch selects ME 12 specification defined at common code and removes cannonlake SoC specific ME code and data structures. BUG=b:260309647 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ifc64cf63736bb730492b1732a22669a0415816a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73140 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-24soc/intel/jsl: Select CSE defined ME spec version for jasperlakeDinesh Gehlot
Jasperlake based SoCs uses Intel's Management Engine (ME), version 13. This patch selects ME 13 specification defined at common code and removes jasperlake SoC specific ME code and data structures. BUG=b:260309647 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Icf4bc651e94d6ec977ed8f2381d7184337dc1ea5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73139 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-24soc/intel/tgl: Select CSE defined ME spec version for tigerlakeDinesh Gehlot
Tigerlake based SoCs uses Intel's Management Engine (ME), version 15. This patch selects ME 15 specification defined at common code and removes tigerlake SoC specific ME code and data structures. BUG=b:260309647 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: If4fbfd7c591794ed945c1e9e8487a9e9723c7551 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73138 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-24soc/intel/mtl: Select CSE defined ME spec version for meteorlakeDinesh Gehlot
Meteorlake based SoCs uses Intel's Management Engine (ME), version 18. This patch selects ME 18 specification defined at common code and removes meteorlake SoC specific ME code and data structures. BUG=b:260309647 Test=Build verified for rex. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I36ee66f94f0c37ab6a134e79e49da9abc83b93cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/73137 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-24soc/intel/cmn/block/cse: ME source code at common locationDinesh Gehlot
This patch adds ME specific source code at common location in order to reduce maintenance efforts at SoC level and improve readability. The functionality and code are redundant for various SoC platforms and require more maintenance. BUG=b:260309647 Test=Build verified for brya and rex. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ic6622662fd3b8bcc9d9ac8bd6ffa732f5d78801a Reviewed-on: https://review.coreboot.org/c/coreboot/+/73133 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-24soc/intel/cmn: Support for ME spec versions for SoCs at common codeDinesh Gehlot
This patch includes ME specification datastructures for various ME versions. Including the ME specification in common code will help current and future SoC platforms to select the correct version based on the applicable configuration. It might be also beneficial if two different SoC platforms would like to use the same ME specification and not necessarily share the same SoC directory. BUG=b:260309647 Test=Build verified for brya and rex. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I83df41d7180d2df419849a0c01c728ff0fe75378 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73129 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-24soc/intel/cmn: Include ME specification configuration at commonDinesh Gehlot
This patch includes ME specification configuration for various versions, which will allow SoCs to get ME support by selecting the correct version. BUG=b:260309647 Test=Build verified for brya and rex. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I817d14e52b0d353bbb4316d6362fcb80cbec3cda Reviewed-on: https://review.coreboot.org/c/coreboot/+/73128 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-23soc/intel/elkhartlake/gpio.c: Fix GPD reset mapMichał Żygowski
The reset bit mapping was incorrectly assigned to GPIO groups. The reset mapping for Community 0 actually reflects the GPD reset mapping. Change the Community 0 reset mapping to the correct default map and fix the GPD reset mapping. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I2b9d093ca7ea0f5087f49671ca457c0b45927918 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-23soc/intel/xeon_sp/uncore.c: mark TSEG/SMM region as reservedJonathan Zhang
Change-Id: I5f534a898de4ba58ac7d65c5bd6ee10eafa648e4 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-02-23intel/alderlake: remove skip_mbp_hob SOC chip configKapil Porwal
Introduce at new config option CONFIG_FSP_PUBLISH_MBP_HOB to control the creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP. This new option is hooked with `SkipMbpHob` UPD and is always disabled for RPL & ADL-N based ChromeOS platforms. It is not disabled for ADL-P based platforms because ADL-P FSP relies on MBP HOB for ChipsetInit version for ChipsetInit sync. As ChipsetInit sync doesn't occur if no MBP HOB, so it results S0ix issue. This limitation is addressed in the later platforms so creation of MBP HOB can be skipped for ADL-N and RPL based platforms. This made skip_mbp_hob SOC chip config variable redundant which is also removed as part of this change. BUG=none TEST=Build and boot to Google/Taniks. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ia396b633a71aedf592c45b69063ee0528840fd2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-02-23Revert "soc/intel/adl: Select CSE defined ME spec version for alderlake"Lean Sheng Tan
This reverts commit 272c9c07bd9c7dcd684614c67487504ce06f7a36. Reason for revert: Sorry was going to give +2 but pressed the submit button and accidentally merged this out of train. Change-Id: I8a2c6407832bdcf3d475209356501f8fc3672f6b Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73213 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-23soc/intel/adl: Select CSE defined ME spec version for alderlakeDinesh Gehlot
Alderlake based SoCs uses Intel's Management Engine (ME), version 16. This patch selects ME 16 specification defined at common code and removes alderlake SoC specific ME code and data structures. BUG=b:260309647 Test=Build verified for brya. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I94cb8a9cbb6167d1a11a012efbd6a135a8692969 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73135 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-23soc/intel: Use common codeflow for MP initArthur Heymans
This fixes MP init on xeon_sp SoCs which was broken by 69cd729 (mb/*: Remove lapic from devicetree). Alderlake cpu code was linked in romstage but unused so drop it. Change-Id: Ia822468a6f15565b97e57612a294a0b80b45b932 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-22soc/intel/xeon_sp/spr: Add common device treeTim Chu
Add common device tree used for EGS platform. Also add register setting shared for all EGS platform. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I812f621ee9d1643fd4fa35df92443d64f7aaabc3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Simon Chou <simonchou@supermicro.com.tw> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-02-20soc/intel/{tgl,adl}: Hook up D3ColdEnable UPD to D3COLD_SUPPORTSean Rhodes
Select NO_S0IX_SUPPORT for `starlabs/starbook` and `atlas/prodrive` so their configurations are unchanged. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I718952165daa6471f11e8025e745fe7c249d3b46 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72800 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-20soc/intel/rtd3: Hook up supported states to KconfigSean Rhodes
Report `4` in `_S0W` only when D3COLD_SUPPORT is enabled, as if it is not, it will break S3 exit. When D3COLD_SUPPORT is not enabled, return `3` (D3Hot). This fixed S3 exit on both TGL and ADL. Tested on StarBook Mk V and Mk VI. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3a4b89132b594ad568a5851137575f921f8e2a2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/72765 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-19soc/intel/xeon_sp/finalize.c: Set BIOS_DONE MSR as applicableTim Chu
If BIOS_DONE MSR is supported, set it after ReadyToBoot, because FSP programs certain registers via Notify phase ReadyToBoot and it cannot be modified by FSP after coreboot has set BIOS_DONE MSR, therefore we try to set BIOS_DONE MSR as late as possible to avoid this. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Change-Id: I4f19a7c54818231ebbccd2b6f8b23f47b117eb1f Reviewed-on: https://review.coreboot.org/c/coreboot/+/71964 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-02-19soc/intel/common/block/fast_spi: Add SPI Vendor Component LockJonathan Zhang
Add fast_spi_set_vcl() to be called by the SOC lockdown function if SPI Vendor Specific Component Capabilities are desired. Change-Id: I6d9b58e90fa16c539b90c6b961862e97e1bf29a2 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72478 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-18soc/intel/meteorlake: Add PM Energy Report feature optionYong Zhi
This patch adds enable/disable FSP DisableEnergyReport feature option to be used in devicetree for power instrument purpose. BUG=None Branch=None Test=Build and boot MTL RVP. Signed-off-by: Yong Zhi <yong.zhi@intel.com> Change-Id: I58d4aea28ee2561d2ed73260c40cb22ce3fdd135 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-02-17soc/intel/common/block/graphics: Hook up all ADL-S IGD PCI IDsMichał Żygowski
Some users of MSI Z690-A board reported non-working IGD display during post using various CPUs. As not all PCI IDs were hooked, coreboot didn't detect GOP-provided framebuffer nor passed the framebuffer information to the payload, causing a black screen. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I07584e07182ee56b61b6f751100431589d1cbe83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elias Souza <eliascontato@protonmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17soc/intel/common/block/smbus/Kconfig: Drop unused ACPI driver Kconfig symbolElyes Haouas
Change-Id: Ic46e1663609068439069f666beca17ed76c679f0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69331 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17treewide: Remove unuseful "_ART : Active Cooling Relationship Table"Elyes Haouas
Change-Id: Ief8dd9c7f7b82e1cd62de5bc1a361432b0eac4ca Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17treewide: Remove unuseful "_ADR: Address" commentElyes Haouas
Change-Id: Ib968fe7f9f95e8f690b46b868fd7d6f9332b4c9a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72664 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17treewide: Remove unuseful "_UID: Unique ID" commentElyes Haouas
Change-Id: I150a4ed94bcaead6eb45f1c4b4952ae6957e0940 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17treewide: Remove unuseful "_CID: Compatible ID" commentElyes Haouas
Change-Id: I7db69e2faf412b9c6732f6dfc362d5774094ef27 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17treewide: Remove unuseful "_HID: Hardware ID" commentElyes Haouas
Change-Id: I5eb1424e9e6c1fbf20cd0bf68fbb52e1ec97f905 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17soc/intel/cmn/block/acpi: enable BERT table without crashlogJonathan Zhang
Besides crashlog, there's also other errors such as MCA error, which should be recorded in BERT table. With current code, BERT table is not generated if crashlog is not enabled. Add if statement for SOC_INTEL_CRASHLOG so that MCA error can be recorded in BERT table when crashlog is not supported. For some server mainboard, crashlog is supported through BMC instead of host firmware. Also check if BERT region is generated when crashlog is not enabled. Change-Id: I323ca889eef2b246fc4e062582d2d11b4213316f Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-02-17soc/intel/xeon_sp: move PCH specific code into lbg directoryJonathan Zhang
pmc_lock_smi() and pmc_lockdown_config() have PCH specific implementations. Move them from common lockdown.c and pmc.c into lbg/soc_pmutil.c. Move sata_lockdown_config() and spi_lockdown_config() to lbg/lockdown.c. While here, fix some coding style issues. Change-Id: I9b357ce877123530dd5c310a730808b6e651712e Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Simon Chou <simonchou@supermicro.com.tw> Reviewed-by: Jian-Ming Wang <jianmingW@supermicro.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-02-17soc/intel/meteorlake: Improve `incomplete` debug messageSubrata Banik
This patch improves `incomplete` debug messages for missing ACPI name PCI devices. Additionally, using the proper PCI device B:D:F to locate the device with the missing ACPI name. Finally, modify the msg time from Debug to Warning to make it more purposeful. TEST=Able to build and boot google/rex. Without this patch: ``` [DEBUG]  dev->path.devfn=10 [DEBUG]  dev->path.devfn=a2 [DEBUG]  dev->path.devfn=b0 ``` With this patch: ``` [WARN]  Missing ACPI Name for PCI: 00:02.0 [WARN]  Missing ACPI Name for PCI: 00:14.2 [WARN]  Missing ACPI Name for PCI: 00:16.0 ``` Change-Id: I605e59de8cbec18c9a56eaa6e90a34f36ea4cdd9 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73072 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-02-17soc/intel/cmn/acpi/pep: Add PCI device number for warning msgSubrata Banik
This patch fixes the wrong warning msg around `Unknown min d_state` with having proper PCI Bus/Device/Function number to help to parse the log better. With this patch: [WARN ]  Unknown min d_state for 20 [WARN ]  Unknown min d_state for 50 [WARN ]  Unknown min d_state for 98 [WARN ]  Unknown min d_state for 9a [WARN ]  Unknown min d_state for f9 With this patch: [WARN ]  Unknown min d_state for PCI: 00:04.0 [WARN ]  Unknown min d_state for PCI: 00:0a.0 [WARN ]  Unknown min d_state for PCI: 00:13.0 [WARN ]  Unknown min d_state for PCI: 00:13.2 [WARN ]  Unknown min d_state for PCI: 00:1f.1 Change-Id: Iccaf26882ce5998469b2be6cf5bc7082f193cb29 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-02-16soc/intel/elkhartlake/fsp_params.c: wire up remaining ddc paramsMichał Kopeć
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Change-Id: I434c22cd784e24c76bc47aee8728d28255b762db Reviewed-on: https://review.coreboot.org/c/coreboot/+/72405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-16soc/intel/common/block/pcie/rtd3: Fix root port _ON logicCliff Huang
_ON() calls _STA() at the beginning. If _STA() indicates the device is ON, it exits immediately. The solution is to move this _STA() check into the ONSK logic. In general cases, ONSK remains '0'. NOTE: RTD3 provides a way to skip _OFF() and _ON() methods following by a device reset such as WWAN device. When such device calls its _RST(), it increments OFSK. When the following _OFF() is called, it was scheduled to skip, it will also increments ONSK. Similarly, when the following _ON() is called, it checks if the previous _OFF was skipped or not. If skipped, it needs to do the same. In normal suspend/resume cases, these two variables remains '0'. No _OFF() and _ON() calls are skipped. entire generated code: Method (_ON, 0, Serialized) // _ON_: Power On { If ((ONSK == Zero)) { Local0 = \_SB.PCI0.RP01.RTD3._STA () If ((Local0 == One)) { Return (One) } Acquire (\_SB.PCI0.R3MX, 0xFFFF) EMPG = Zero Local7 = 0x06 While ((Local7 > Zero)) { If ((AMPG == Zero)) { Break } Sleep (0x10) Local7-- } Release (\_SB.PCI0.R3MX) \_SB.PCI0.PMC.IPCS (0xAC, Zero, 0x10, 0x00000020, 0x00000020, 0x00000020, 0x00000020) \_SB.PCI0.STXS (0x015E) If ((NCB7 == One)) { L23R = One Local7 = 0x14 While ((Local7 > Zero)) { If ((L23R == Zero)) { Break } Sleep (0x10) Local7-- } NCB7 = Zero Local7 = 0x08 While ((Local7 > Zero)) { If ((LASX == One)) { Break } Sleep (0x10) Local7-- } } } Else { ONSK-- } } BUG=b:249931687 BUG=b:241850118 TEST=Use above functions and check the generated SSDT table after OS boot. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Id1ea2e78e98d334a90294ee6cdd14ae2de9b9b62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72826 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-16soc/intel/xeon_sp: add ebg (Emmitsburg PCH) directoryTim Chu
EBG (Emmitsburg) PCH is used in Intel SPR-SP chipset. These changes are in accordance with the documentation: * Intel(R) Emmitsburg Platform Controller Hub External Design Specification. Document Number: 606161 * Emmitsburg PCH BIOS Specification. Document Number: 631063. Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I393c1df75a344519fca7d680116f41f5f8bd9e87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2023-02-16soc/intel/cmn/gfx: Skip warning msg in ChromeOS normal modeSubrata Banik
This patch ensures avoiding displaying wrong warning msg as `Graphics hand-off block not found` during ChromeOS normal mode booting as FSP is not executing GFX PEIM hence, GFX hand-off HOB is expected to be missing.  TEST=Able to build and boot google/rex in normal mode w/o having warning msg.  Change-Id: Ia9192129852195f6183c0c43369cd33b253f9140 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-02-15soc/intel/alderlake: Disable package C-state demotion for Raptor LakeAnil Kumar
While executing S0ix tests on Raptor Lake boards, we observed CPU fails to enter suspend state, causing failure. As a workaround, disable package C-state demotion, till this issue is fixed in ucode. BUG=268296760 BRANCH=firmware-brya-14505.B TEST=Boot and verified that S0ix issue is resolved. Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: Ie50e1024f4118d82d2ad762b54fa722c43990d12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72942 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-02-15soc/intel/adl: Correct wrongly reported ADL PCH SKULean Sheng Tan
Per Intel 600 & 700 series PCH EDS (626817), these PCH IDs belongs to ADL not RPL, though some RPL SoCs are also using ADL PCH. Hence correct the name reporting to avoid confusion when ADL SoCs were used. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I61a608e2c99b1d60a99d6ad734b396676f3a2ab2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72999 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-14soc/intel/alderlake: Add missing SATA DSDT devicePatrick Rudolph
Add "SATA" to DSDT as it's referenced by Intel PEP SSDT. Fixes warning shown in Linux: ACPI Error: AE_NOT_FOUND, While resolving a named reference package element - \_SB_.PCI0.SATA (20220331/dspkginit-438) Change-Id: I65a1d17bce246022859f011cdc4712e1206a98fe Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72762 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-14soc/intel/meteorlake: Hook up `SkipExtGfxScan` FSP-M UPDSubrata Banik
This patch allows override to the `SkipExtGfxScan` UPD. Ideally a platform with an on-board graphics device should skip scanning external GFX devices aka set this UPD to `1`. BUG=b:228002764 TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I00e15b71ed67119df9ca6f98a750ede109ff33fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/72947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-02-13soc/intel/alderlake: Fix ACPI name for DPTFCoolStar
The correct ACPI device for DPTM is TCPU; fixing this puts the participant devices under the correct parent device, and allows Windows to properly go into S0ix. TEST=builb/boot Win11 on google/banshee, verify Si0x functional. Change-Id: I1b3e2655d4d42e008dead9bc87b73ce02868fdfa Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-02-13soc/intel/xeon_sp/chip_common.c: check SOC_INTEL_PCIE_64BIT_ALLOCJonathan Zhang
Some FSPs (such as SPR-SP FSP) support SOC_INTEL_PCIE_64BIT_ALLOC. In such case, is_pci64bit_alloc() return 1. Change-Id: Ic33967255baf4675cd72e0db32ef3fb7f5658296 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72441 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-10soc/intel/common/block/fast_spi: Add SPI BIOS decode lockTim Chu
The SPI BIOS decode lock bit needs to be set, according to Intel EBG EDS dodcumentation. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I3366817b42a5878f16575698ebc546fa7852e285 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2023-02-10soc/intel/{common, meteorlake}: Add support for new MCHSridhar Siricilla
The patch adds support for new Meteor Lake MCH (ID:0x7d16). TEST=Build and boot the system having MCH ID:0x7d16. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ib0c9ce5c58e4bdec5e7245840f0892d651922cd9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Usha P <usha.p@intel.com>
2023-02-09mb/prodrive/hermes: Hook up wake on USB optionAngel Pons
Hook up the `wake_on_usb` EEPROM setting so that it works as intended. TEST=Keysmash on a USB keyboard, verify Hermes does not wake from S3. Change-Id: I81531b90abae6a62754ea66c47e934e1f440bda2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72906 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-09arch/x86/include/cpu: introduce CPU_TABLE_END CPU table terminatorFelix Held
Instead of having a magic entry in the CPU device ID table list to tell find_cpu_driver that it has reached the end of the list, introduce and use CPU_TABLE_END. Since the vendor entry in the CPU device ID struct is compared against X86_VENDOR_INVALID which is 0, use X86_VENDOR_INVALID instead of the 0 in the CPU_TABLE_END definition. TEST=Timeless build for Mandolin results in identical image. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Angel Pons <th3fanbus@gmail.com> Change-Id: I0cae6d65b2265cf5ebf90fe1a9d885d0c489eb92 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72888 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-09src/soc/intel/common/block/pcie/rtd3: Fix root port _STA logicCliff Huang
When enable_gpio is used as active low output, the _STA returns incorrect value. Also, simply the logic for _STA method. When enable pin is used for _STA: | polarity | tx value| get_tx_gpio() | State | | active high | 0 | 0 | 0 | | active high | 1 | 1(active) | 1 | | active low | 0 | 1(active) | 1 | | active low | 1 | 0 | 0 | When reset pin is used for _STA: | polarity | tx value| get_tx_gpio() | State | | active high | 0 | 0 | 1 | | active high | 1 | 1(active) | 0 | | active low | 0 | 1(active) | 0 | | active low | 1 | 0 | 1 | Generated _STA method: Ex: for using active low power enable GPIO pin GPPC_H17: Method (_STA, 0, NotSerialized) // _STA: Status { Local0 = \_SB.PCI0.GTXS (0x5C) Local0 ^= One Return (Local0) } TEST=Check the SSDT when booted to OS. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Ie6f1e7a5b3e9fd0ea00e1e5b54058a14c6e9e09e Reviewed-on: https://review.coreboot.org/c/coreboot/+/72421 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-09treewide: Remove repeated wordsElyes Haouas
Found by linter Change-Id: I7a49cce0b56cf83d0e4490733f9190284a314c4a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-09soc/intel/common/block/gpio/gpio.c: Remove unnecessary line continuationElyes Haouas
Also remove unnecessary whitespace before "\n" Change-Id: Ia2c8fcb82658ed3e247759535d3112270d46e65d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-09soc/intel/meteorlake: Remove unsupported hybrid_storage_mode configSridhar Siricilla
The patch removes hybrid_storage_mode variable from soc_intel_meteorlake_config struct since hybrid storage is no longer supported on Meteor Lake platform. TEST=Verify the build for Rex board Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I40ec3775b827ab6e1ebd4778c6c8e13eac1944e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-09Revert "device: Add Kconfig options for D3COLD_SUPPORT and NO_S0IX_SUPPORT"Felix Singer
This reverts commit d6e04aa00bc5a8912a041a569eb57f6962d1119a. Reason for revert: Breaks master. Change-Id: If7daeaaffe3f9ae9f5e2fbecef5817b9b62827d3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72917 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-02-08device: Add Kconfig options for D3COLD_SUPPORT and NO_S0IX_SUPPORTSean Rhodes
Add NO_S0IX_SUPPORT for boards that do not support, or do not want to support S0IX. As all the boards in the tree that do this, don't support D3Cold, add D3COLD_SUPPORT that defaults to `n` when NO_S0IX_SUPPORT is selected to disable D3Cold support. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I04abc7efe2db06ae6daba9e09835441b62ee44f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-08arch/x86/cpu: introduce and use device_match_maskFelix Held
Instead of always doing exact matches between the CPUID read in identify_cpu and the device entries of the CPU device ID table, offer the possibility to use a bit mask in the CPUID matching. This allows covering all steppings of a CPU family/model with one entry and avoids that case of a missing new stepping causing the CPUs not being properly initialized. Some of the CPU device ID tables can now be deduplicated using the CPUID_ALL_STEPPINGS_MASK define, but that's outside of the scope of this patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0540b514ca42591c0d3468307a82b5612585f614 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72847 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-02-08soc/intel/{tgl,adl}/acpi: Unify the way D3Cold is enabledSean Rhodes
Both Alder Lake and Tiger Lake have Kconfig options for S3, which disables support for D3Cold. Unify these so that they are easier to compare. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I6eaba99e5483053a91ca20df2b7788edac5d65b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72798 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>