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path: root/src/soc/intel/tigerlake
AgeCommit message (Expand)Author
2020-09-26arch/x86: Introduce `ARCH_ALL_STAGES_X86_32`Angel Pons
2020-09-25soc/intel/tigerlake: Remove extra '_' from GPIO PIN nameSubrata Banik
2020-09-25soc/intel/{jsl,tgl}: Refactor gpio_op.aslSubrata Banik
2020-09-24soc/intel/tigerlake: Add support for CnviBtCore and CnviBtAudioOffloadJohn Zhao
2020-09-23soc/intel/tigerlake: Configure FSP UPDs for minimum assertion widthsJamie Ryu
2020-09-22Revert "soc/intel: Refactor do_global_reset() function"Furquan Shaikh
2020-09-21src/soc/intel: Drop unneeded empty linesElyes HAOUAS
2020-09-21soc/intel: Refactor do_global_reset() functionSubrata Banik
2020-09-21soc/intel: rename get_prmrr_sizeMichael Niewöhner
2020-09-19soc/intel/common/block/cse: Refactor cse_request_global_reset() functionSubrata Banik
2020-09-17mb/volteer: Select USE_CAR_NEM_ENHANCED_V2 for Tigerlake QS basedShreesh Chhabbi
2020-09-14soc/intel/{cnl,icl,jsl,tgl}: Clean up chip.hSubrata Banik
2020-09-14soc/intel/tigerlake: Increase PRERAM_CBMEM_CONSOLE_SIZE to 8KBAnil Kumar
2020-09-14soc/intel/tigerlake: Select USE_CAR_NEM_ENHANCED_V2 for tigerlakeShreesh Chhabbi
2020-09-11soc/intel/tigerlake: Clean up systemagent.hSubrata Banik
2020-09-10soc/intel/tigerlake: Maintain consistent tab in iomap.hSubrata Banik
2020-09-08soc/intel/tigerlake: Skip GPIO configuration from FSPSrinidhi N Kaushik
2020-09-08soc/intel/tigerlake: Add SMRR Locking supportTim Wawrzynczak
2020-09-06soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by defaultMichael Niewöhner
2020-09-04soc/intel/{jasperlake,tigerlake}/Kconfig: Drop redundant 'select CPU_INTEL_CO...Elyes HAOUAS
2020-09-04soc/intel/tigerlake: Remove unused PID_SDX macroSubrata Banik
2020-09-02soc/intel/tigerlake: Add mainboard hook for overriding SoC configJes Klinke
2020-08-28soc/intel/tigerlake: add ddr4-spd-empty.hexAaron Durbin
2020-08-28util: Add memory parts needed by zork boardsRob Barnes
2020-08-28util/gen_spd: translate DeviceBusWidth to die bus widthNick Vaccaro
2020-08-28util: rename lp4x spds to include "lp4x-" in nameNick Vaccaro
2020-08-28util: volteer/dedede: move generic SPDs to common locationNick Vaccaro
2020-08-26soc/intel/tigerlake: Rename pch_init() codeAlexey Buyanov
2020-08-25util: Add spd_tools to generate DDR4 SPDs for TGL boardsNick Vaccaro
2020-08-24soc/intel/tigerlake: Fix IPU and Vtd configRavi Sarawadi
2020-08-21soc/intel/tigerlake: Enable long cr50 ready pulsesJes Klinke
2020-08-18elog: rename ELOG_WAKE_SOURCE_GPIO to ELOG_WAKE_SOURCE_GPEAaron Durbin
2020-08-18src: Remove unneded whitespace before tabElyes HAOUAS
2020-08-17soc/intel/tigerlake: Allow fine grained control of S0iX statesJes Klinke
2020-08-14soc/intel/tigerlake: Increase PRERAM_CBMEM_CONSOLE_SIZE to 5KBRavi Sarawadi
2020-08-12soc/intel/tigerlake: Add IRQs for LPSS uartPatrick Rudolph
2020-08-09soc/intel/{icl.tgl,jsl}: Remove SMRAM register programmingAamir Bohra
2020-08-07soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASESubrata Banik
2020-08-06soc/intel/tigerlake: add common routine for DDR initNick Vaccaro
2020-08-05{nb,soc}/intel: Use get_current_microcode_rev() for ucode versionSubrata Banik
2020-08-03soc/intel/tigerlake: Invoke PCIe root port swappingCaveh Jalali
2020-08-01soc/intel/{icl,jsl,tgl}: Remove SkipMpInit UPD as deprecatedSubrata Banik
2020-07-29soc/intel/tigerlake: Configure TCSS D3Hot and D3ColdJohn Zhao
2020-07-29soc/intel/tigerlake: Set default USB3 de-emphasis to -3.5dBDuncan Laurie
2020-07-28soc/intel/tigerlake: Simplify is-device-enabled checksFelix Singer
2020-07-26soc/intel/tigerlake: Disable CPU PCIe in FSPShaunak Saha
2020-07-26soc/intel/tigerlake: Disable VT-d and no DMAR table for pre-QS platformJohn Zhao
2020-07-26src/soc/intel: Add include <types.h>Elyes HAOUAS
2020-07-26src: Update bare access to BOOL CONFIG_ vals to CONFIG()Martin Roth
2020-07-26cpu,soc/intel: Drop select SMPKyösti Mälkki
2020-07-26src: Remove unused 'include <cbmem.h>'Elyes HAOUAS
2020-07-26src: Remove extra lines in license headerElyes HAOUAS
2020-07-25soc/intel/tigerlake: Update Pkg C-State latenciesRavi Sarawadi
2020-07-25soc/intel/tigerlake: Set power limits for Tiger Lake Y-SKUSumeet R Pawnikar
2020-07-25soc/intel/tigerlake: Update Tiger Lake SA IDsDerek Huang
2020-07-21soc/intel/tigerlake: Select PLATFORM_USES_FSP2_2Subrata Banik
2020-07-21src: Use ACPI macrosElyes HAOUAS
2020-07-15soc/intel/tigerlake: Hook up SATA Port Enable DITO UPDsShaunak Saha
2020-07-14src: Remove unused 'include <stdint.h>Elyes HAOUAS
2020-07-12soc/intel/tigerlake: Move tco_configure to bootblockTim Wawrzynczak
2020-07-12soc/intel/tigerlake: Configure Type-C Input Output Manager(IOM) deviceJohn Zhao
2020-07-12soc/intel/tigerlake: Add Type-C IOM base address and size macroJohn Zhao
2020-07-12soc/intel/tigerlake: Add new IGD deviceRavi Sarawadi
2020-07-09mainboard/intel/tglrvp: Remove unused PrmrrSize chip configSubrata Banik
2020-07-07soc/intel/common/block: Add new block DTTTim Wawrzynczak
2020-07-07soc/intel/tigerlake: Disable Thunderbolt PCIe root ports bus masterJohn Zhao
2020-07-07soc/intel/{tiger,jasper}lake: Add IPU to soc_acpi_nameTim Wawrzynczak
2020-07-07lp4x: Add new memory parts and generate SPDsDavid Wu
2020-07-06soc/intel: Drop unused `#include <reg_script.h>`Angel Pons
2020-07-04soc/intel/tigerlake: Remove unused EHL DID from TGL SoCSubrata Banik
2020-07-03soc/intel/tigerlake: Disable hybrid storage mode in CSE Lite RO bootJamie Ryu
2020-07-03drivers/intel/pmx_mux: Remove redundant declarationKyösti Mälkki
2020-07-01soc/intel/tigerlake: Add platform wide _OSC capabilities for USB4John Zhao
2020-06-30tigerlake: enable tcc_offset functionalitySumeet R Pawnikar
2020-06-30ACPI: Drop typedef global_nvs_tKyösti Mälkki
2020-06-30soc/intel/tigerlake: Add CpuReplacementCheck to chip optionsJamie Ryu
2020-06-30soc/intel/tigerlake: Avoid NULL pointer dereferenceJohn Zhao
2020-06-30src: Remove whitespaces before tabsElyes HAOUAS
2020-06-29soc/intel/tigerlake: Run pmc_set_acpi_mode() during .init in pmc_opsWilliam Wei
2020-06-25drivers/intel/fsp2_0: decouple FSP_PEIM_TO_PEIM_INTERFACE from FSP 2.1Jonathan Zhang
2020-06-24soc/intel/tigerlake: Fix unresolved symbol CDW1 errorJohn Zhao
2020-06-22soc/intel/tigerlake: Add CmdMirror option in chip.hDavid Wu
2020-06-22mb/google/volteer: Override power limits with SKU-specific limitsTim Wawrzynczak
2020-06-22soc/intel/tigerlake: Update platform.asl to ASL2.0 syntaxV Sowmya
2020-06-19soc/intel/tigerlake: Update TCSS for SW CM supportJohn Zhao
2020-06-19tigerlake: add unique acpi device ids for dptfSumeet R Pawnikar
2020-06-18soc/intel/tigerlake: Enable FSP-S compressionKarthikeyan Ramasubramanian
2020-06-17soc/soch/intel/tigerlake: Integrate PCIe hot-plug config UPDWonkyu Kim
2020-06-16soc/intel/common: Replace smm_soutbridge_enable(SMI_FLAGS)Kyösti Mälkki
2020-06-16arch/x86: Create helper for APM_CNT SMI triggersKyösti Mälkki
2020-06-14soc/intel/tigerlake: enable CPU_INTEL_COMMONAlex Levin
2020-06-12soc/intel/tigerlake: Add devicetree support to change PCH VR settingsVenkata Krishna Nimmagadda
2020-06-10soc/intel/tigerlake: Add Hot-Plug and PME event handlers for ThunderboltJohn Zhao
2020-06-10ACPI: Remove Kconfig COMMON_FADTKyösti Mälkki
2020-06-09soc/intel/tigerlake: Set FSPS UPD ITbtConnectTopologyTimeoutInMsJohn Zhao
2020-06-09soc/intel/tigerlake: Increase heap sizeDuncan Laurie
2020-06-08spd/lp4x: Set manufacturer part name to blank (0x20)Furquan Shaikh
2020-06-07soc/intel/tigerlake/acpi: Update gpio_op.asl to ASL2.0 syntaxVenkata Krishna Nimmagadda
2020-06-06soc/intel/tigerlake: Add CPU ID for TGL B0Jamie Ryu
2020-06-06lp4x: Add new memory parts and generate SPDsFurquan Shaikh