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authorSubrata Banik <subrata.banik@intel.com>2020-09-24 18:23:23 +0530
committerSubrata Banik <subrata.banik@intel.com>2020-09-25 03:02:49 +0000
commit8d4176109d404dbbaf4689281ccec635c1070e99 (patch)
tree2643b92882a2a9d4a37777f9f134ec647521e3b0 /src/soc/intel/tigerlake
parent63ee16075e7e4dee90c0cb9b05caeb91f77bf1e5 (diff)
soc/intel/{jsl,tgl}: Refactor gpio_op.asl
Also align GPMO ASL function with TGL. Change-Id: Ia40af2cba9867838a1f99141481a5e78cffa0111 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/tigerlake')
-rw-r--r--src/soc/intel/tigerlake/acpi/gpio_op.asl12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/soc/intel/tigerlake/acpi/gpio_op.asl b/src/soc/intel/tigerlake/acpi/gpio_op.asl
index f7332aa137..9b9dc4477c 100644
--- a/src/soc/intel/tigerlake/acpi/gpio_op.asl
+++ b/src/soc/intel/tigerlake/acpi/gpio_op.asl
@@ -43,7 +43,7 @@ Method (STXS, 1, Serialized)
{
VAL0, 32
}
- VAL0 = PAD_CFG0_TX_STATE | VAL0
+ VAL0 |= PAD_CFG0_TX_STATE
}
/*
@@ -57,7 +57,7 @@ Method (CTXS, 1, Serialized)
{
VAL0, 32
}
- VAL0 = ~PAD_CFG0_TX_STATE & VAL0
+ VAL0 &= ~PAD_CFG0_TX_STATE
}
/*
@@ -97,9 +97,9 @@ Method (GTXE, 2, Serialized)
}
If (Arg1 == 1) {
- VAL0 = ~PAD_CFG0_TX_DISABLE & VAL0
+ VAL0 &= ~PAD_CFG0_TX_DISABLE
} ElseIf (Arg1 == 0){
- VAL0 = PAD_CFG0_TX_DISABLE | VAL0
+ VAL0 &= PAD_CFG0_TX_DISABLE
}
}
@@ -119,8 +119,8 @@ Method (GRXE, 2, Serialized)
}
If (Arg1 == 1) {
- VAL0 = ~PAD_CFG0_RX_DISABLE & VAL0
+ VAL0 &= ~PAD_CFG0_RX_DISABLE
} ElseIf (Arg1 == 0){
- VAL0 = PAD_CFG0_RX_DISABLE | VAL0
+ VAL0 |= PAD_CFG0_RX_DISABLE
}
}