| Age | Commit message (Expand) | Author |
|---|
| 2021-10-12 | soc/intel/*/cpu.c: Add missing space in comment | Angel Pons |
| 2021-10-11 | soc/intel/tigerlake: Add ACPI addition for USB4/TBT latency optimization | John Zhao |
| 2021-10-07 | soc/intel/tigerlake: Hook up GMA ACPI brightness controls | Tim Crawford |
| 2021-10-05 | src/soc to src/superio: Fix spelling errors | Martin Roth |
| 2021-10-01 | soc/tigerlake: Make IO decode / enable register configurable | Sean Rhodes |
| 2021-09-29 | soc/intel: Drop unnecessary `select REG_SCRIPT` | Angel Pons |
| 2021-09-29 | soc/intel/{cnl,jsl,tgl,ehl,adl}: rename PMC device init/enable callbacks | Michael Niewöhner |
| 2021-09-23 | soc/intel/tgl: correct wrong gpio GPI enable register base offset | Michael Niewöhner |
| 2021-09-23 | soc/intel/{xeon-sp,icl,tgl,jsl,ehl}: add NMI_{EN,STS} registers | Michael Niewöhner |
| 2021-09-23 | mb/google/volteer: Migrate volteer to use SPD files under spd/ | Reka Norman |
| 2021-09-20 | soc/intel/tigerlake: Clear RTC_BATTERY_DEAD | Tim Wawrzynczak |
| 2021-09-20 | soc/intel/{common,tgl,adl}: guard TME Kconfig option by SoC support | Michael Niewöhner |
| 2021-09-16 | drivers/intel/fsp2_0: Refactor MultiPhaseSiInit API calling method | Subrata Banik |
| 2021-09-13 | soc/intel/tgl: Enable USB4 resources based on common Kconfig | Furquan Shaikh |
| 2021-09-10 | soc/intel/tigerlake: Switch to runtime generation of Intel Power Engine | Tim Wawrzynczak |
| 2021-09-10 | soc/intel/tigerlake: Move LPM functions to new file | Tim Wawrzynczak |
| 2021-09-08 | cpu/x86/tsc: Deduplicate Makefile logic | Angel Pons |
| 2021-09-02 | soc/intel/tigerlake: Set MAX_CPUS for TGL-H to 16 | Tim Crawford |
| 2021-08-26 | soc/intel/tigerlake: Lock PAM registers in finalize | Tim Wawrzynczak |
| 2021-08-25 | soc/intel/tigerlake: Hook up ucode for TGL-H | Tim Crawford |
| 2021-08-24 | soc/intel/tigerlake: Add USB ACPI devices for PCH-H | Jeremy Soller |
| 2021-08-24 | soc/intel/tigerlake: Add SPI_DMI_DESTINATION_ID for PCH-H | Jeremy Soller |
| 2021-08-24 | soc/intel/tigerlake: Set UserBd to recommended default for PCH-H | Jeremy Soller |
| 2021-08-24 | soc/intel/tgl: Add PCR_PSF3_T0_SHDW_PMC_REG_BASE for PCH-H | Jeremy Soller |
| 2021-08-24 | soc/intel/tigerlake: Add TGL-H PEG ports | Jeremy Soller |
| 2021-08-24 | soc/intel/tigerlake: Add PCIe root ports for PCH-H | Jeremy Soller |
| 2021-08-24 | soc/intel/tigerlake: Add PCH-H GPIO definitions | Jeremy Soller |
| 2021-08-24 | soc/intel/tigerlake: Add PCH-H PMC GPE group definitions | Jeremy Soller |
| 2021-08-24 | soc/intel/tigerlake: Add PCH-H chipset devicetree | Jeremy Soller |
| 2021-08-24 | soc/intel/tigerlake: Add TGL-H power limits | Jeremy Soller |
| 2021-08-24 | soc/intel: Add TGL-H CPUID | Jeremy Soller |
| 2021-08-19 | soc/intel/common: Add TGL-H PCI IDs | Jeremy Soller |
| 2021-08-16 | mb/*/{tglrvp,volteer,deltaur}: move cpu_cluster configuration to chipset.cb | MAULIK V VAGHELA |
| 2021-08-15 | soc/intel/tigerlake: Select SF_MASK_2WAYS_PER_BIT if eNEM is enable | Subrata Banik |
| 2021-08-13 | soc/intel/tgl: Hook up ucode for TGL-U and TGL-R | Tim Crawford |
| 2021-08-12 | soc/intel/tigerlake: Clean up FSP chipset lockdown configuration | Felix Singer |
| 2021-08-12 | soc/intel/tgl: Allow setting PCIe subsystem IDs after FSP-S | Tim Crawford |
| 2021-08-04 | Move post_codes.h to commonlib/console/ | Ricardo Quesada |
| 2021-08-03 | soc/intel/*: Allow configuring 8254 timer via CMOS | Sean Rhodes |
| 2021-07-26 | src/*: Specify type of `CBFS_SIZE` once | Angel Pons |
| 2021-07-19 | soc/intel/common: Rename kconfig PMC_EPOC | Lean Sheng Tan |
| 2021-07-17 | soc/intel/tigerlake: Make use of `cpu/intel/cpu_ids.h' | Subrata Banik |
| 2021-07-15 | soc/intel/tigerlake: Use `is_devfn_enabled()` for Crashlog UPDs | Subrata Banik |
| 2021-07-02 | src: Introduce `ARCH_ALL_STAGES_X86` | Angel Pons |
| 2021-07-01 | soc/intel: Refactor `xdci_can_enable()` function | Angel Pons |
| 2021-06-30 | soc/intel/tigerlake: Send End-of-Post message to CSE | Tim Wawrzynczak |
| 2021-06-30 | soc/intel/common: Move PMC EPOC related code to Intel common code | Lean Sheng Tan |
| 2021-06-30 | src: Move `select ARCH_X86` to platforms | Angel Pons |
| 2021-06-29 | soc/intel/tigerlake: Enable support for common IRQ block | Tim Wawrzynczak |
| 2021-06-28 | soc/intel: Drop casts around `soc_read_pmc_base()` | Angel Pons |
| 2021-06-23 | soc/intel/tigerlake: Use devfn_disable() function for XDCI | Subrata Banik |
| 2021-06-17 | soc/intel/{alderlake,tigerlake}: Fix typo in pmc.h | Werner Zeh |
| 2021-06-16 | soc/intel/tigerlake: Make use of is_devfn_enabled() function | Subrata Banik |
| 2021-06-14 | util: Add DDR4 generic SPD for MT40A512M16TB-062E:R | Wisley Chen |
| 2021-06-10 | soc/intel/tigerlake: Move MAX_CPUS to Kconfig | Andy Pont |
| 2021-06-10 | soc/intel/tigerlake: Hook up FSP repository | Felix Singer |
| 2021-06-07 | cpu/x86: Default to PARALLEL_MP selected | Kyösti Mälkki |
| 2021-06-07 | soc/intel: Drop unused lpss functions | Furquan Shaikh |
| 2021-05-27 | soc/intel/tigerlake: Return TBT PowerResource from PR0 and PR3 | John Zhao |
| 2021-05-26 | soc/intel/tigerlake: Add validity for TBT firmware authentication | John Zhao |
| 2021-05-18 | cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=y | Arthur Heymans |
| 2021-05-14 | soc/intel/tigerlake: Allow devicetree to fill UPD related to TCSS OC | Nick Vaccaro |
| 2021-05-13 | src: Match array format in function declarations and definitions | Patrick Georgi |
| 2021-05-07 | soc/intel/{adl,tgl,jsl}: Enable power button smi after BS_CHIPS_EXIT | Kane Chen |
| 2021-05-07 | soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmaster | Kane Chen |
| 2021-05-06 | soc/intel/tgl,mb/google/volteer: Add API for Type-C aux bias pads | Tim Wawrzynczak |
| 2021-05-06 | soc/intel/tigkerlake: Add IOM PCR PID | Tim Wawrzynczak |
| 2021-05-06 | soc/intel/tigerlake: Add known CPU Port IDs for GPIO communities | Tim Wawrzynczak |
| 2021-05-06 | soc/intel/tigerlake: Add known GPIO virtual wire information | Tim Wawrzynczak |
| 2021-05-03 | soc/intel/*: Update data types for variables holding PCH_DEVFN_* macros | Tim Wawrzynczak |
| 2021-05-03 | device: Switch pci_dev_is_wake_source to take pci_devfn_t | Tim Wawrzynczak |
| 2021-04-26 | soc/intel/tigerlake: Use device ID from pci_devs header file | John Zhao |
| 2021-04-21 | soc/intel: Replace open-coded buffer length calculation | Angel Pons |
| 2021-04-21 | soc/intel: Fix typo in comment | Angel Pons |
| 2021-04-21 | soc/intel/alderlake: rename CONFIG_MAX_PCIE_CLOCKS to CONFIG_MAX_PCIE_CLOCK_SRC | Rizwan Qureshi |
| 2021-04-21 | soc/intel/tigerlake: Fix devices list in the DMAR DRHD structure | John Zhao |
| 2021-04-13 | dptf: Move platform-specific information to `struct dptf_platform_info` | Tim Wawrzynczak |
| 2021-04-06 | intel/tigerlake: Add Acoustic features | Shaunak Saha |
| 2021-03-28 | soc/intel/tigerlake: Fix REG_BASE_SIZE | Tim Wawrzynczak |
| 2021-03-28 | soc/intel/tigerlake: Move TCSS code to intel/common/block | Tim Wawrzynczak |
| 2021-03-27 | soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.h | Subrata Banik |
| 2021-03-22 | soc/intel/tigerlake: Add #include guards to soc/early_tcss.h | Tim Wawrzynczak |
| 2021-03-22 | util: Add DDR4 generic SPD for H4AAG165WB-BCWE | Nick Vaccaro |
| 2021-03-19 | soc/intel/tgl: Add configurable value for PmcUsb2PhySusPgEnable | Derek Huang |
| 2021-03-15 | soc/intel/tigerlake: Remove obsolete CNVi Bluetooth PCI device | Cliff Huang |
| 2021-03-15 | soc/intel/tigerlake: Add CNVi Bluetooth flag at devicetree entry | Cliff Huang |
| 2021-03-12 | soc/intel/*: drop UART pad configuration from common code | Michael Niewöhner |
| 2021-03-05 | soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during boot | Brandon Breitenstein |
| 2021-03-05 | soc/tigerlake: Fix TCSS code to calling back and forth to mainboard and soc | Brandon Breitenstein |
| 2021-03-05 | soc/intel/tigerlake: Fix NULL being passed for response buffer | Furquan Shaikh |
| 2021-03-03 | soc/intel: Factor out common smmrelocate.c | Angel Pons |
| 2021-03-03 | soc/intel/tigerlake: Re-use existing define in CrashLog implementation | Francois Toguo |
| 2021-03-03 | soc/intel: Retype `CnviBtAudioOffload` devicetree option | Angel Pons |
| 2021-03-01 | soc/intel: Drop `bootblock_cpu_init()` function | Angel Pons |
| 2021-03-01 | soc/intel: Drop `romstage_pch_init()` function | Angel Pons |
| 2021-03-01 | soc/intel: Factor out common smbus.h | Angel Pons |
| 2021-03-01 | soc/intel: Factor out common gpe.h | Angel Pons |
| 2021-03-01 | soc/intel: Factor out identical acpigen GPIO helpers | Angel Pons |
| 2021-03-01 | soc/intel: Include gfx.asl from northbridge | Angel Pons |
| 2021-02-24 | soc/intel/*/smmrelocate.c: Sync includes | Angel Pons |
