soc/intel/tgl,mb/google/volteer: Add API for Type-C aux bias pads

TGL boards using the Type-C subsystem for USB Type-C ports without a
retimer attached may require a DC bias on the aux lines for certain
modes to work. This patch adds native coreboot support for programming
the IOM to handle this DC bias via a simple devicetree
setting. Previously a UPD was required to tell the FSP which GPIOs were
used for the pullup and pulldown biases, but the API for this UPD was
effectively undocumented.

BUG=b:174116646
TEST=Verified on volteer2 that a Type-C flash drive is enumerated
succesfully on all ports. Verified all major power flows (boot, reboot,
powerdown and S0ix/suspend) still work as expected.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I70e36a41e760f4a435511c147cc5744a77dbccc0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

4 files changed, 29 insertions, 15 deletions

diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc
index ae6101d880..787aa05c57 100644
--- a/src/soc/intel/tigerlake/Makefile.inc
+++ b/src/soc/intel/tigerlake/Makefile.inc
@@ -37,12 +37,12 @@ ramstage-y += finalize.c
 ramstage-y += fsp_params.c
 ramstage-y += gpio.c
 ramstage-y += lockdown.c
+ramstage-y += me.c
 ramstage-y += p2sb.c
 ramstage-y += pmc.c
 ramstage-y += reset.c
 ramstage-y += soundwire.c
 ramstage-y += systemagent.c
-ramstage-y += me.c
 ramstage-y += xhci.c
 ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog_lib.c
 
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 8c902c3e71..c011093871 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -9,6 +9,7 @@
 #include <intelblocks/gspi.h>
 #include <intelblocks/pcie_rp.h>
 #include <intelblocks/power_limit.h>
+#include <intelblocks/tcss.h>
 #include <soc/gpe.h>
 #include <soc/gpio.h>
 #include <soc/pch.h>
@@ -335,17 +336,14 @@ struct soc_intel_tigerlake_config {
 	uint8_t UsbTcPortEn;
 
 	/*
-	 * IOM Port Config
-	 * If a port orientation needs to be controlled by the SOC this setting must be
-	 * updated to reflect the correct GPIOs being used for the SOC port flipping.
-	 * There are 4 ports each with a pair of GPIOs for Pull Up and Pull Down
-	 * 0,1 are pull up and pull down for port 0
-	 * 2,3 are pull up and pull down for port 1
-	 * 4,5 are pull up and pull down for port 2
-	 * 6,7 are pull up and pull down for port 3
-	 * values to be programmed correspond to the GPIO family and offsets
+	 * These GPIOs will be programmed by the IOM to handle biasing of the
+	 * Type-C aux (SBU) signals when certain alternate modes are used.
+	 * `pad_auxn_dc` should be assigned to the GPIO pad providing negative
+	 * bias (name usually contains `AUXN_DC` or `AUX_N`); similarly,
+	 * `pad_auxp_dc` should be assigned to the GPIO providing positive bias
+	 * (name often contains `AUXP_DC` or `_AUX_P`).
 	 */
-	uint32_t IomTypeCPortPadCfg[8];
+	struct typec_aux_bias_pads typec_aux_bias_pads[MAX_TYPE_C_PORTS];
 
 	/*
 	 * SOC Aux orientation override:
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index 9fbf9bd009..1f1f3652f0 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -23,6 +23,7 @@
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
 #include <soc/soc_chip.h>
+#include <soc/tcss.h>
 #include <string.h>
 
 /* THC assignment definition */
@@ -188,8 +189,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 
 	params->UsbTcPortEn = config->UsbTcPortEn;
 	params->TcssAuxOri = config->TcssAuxOri;
-	for (i = 0; i < 8; i++)
-		params->IomTypeCPortPadCfg[i] = config->IomTypeCPortPadCfg[i];
+
+	/* Explicitly clear this field to avoid using defaults */
+	memset(params->IomTypeCPortPadCfg, 0, sizeof(params->IomTypeCPortPadCfg));
 
 	/*
 	 * Set FSPS UPD ITbtConnectTopologyTimeoutInMs with value 0. FSP will
@@ -460,8 +462,10 @@ void platform_fsp_multi_phase_init_cb(uint32_t phase_index)
 		printk(BIOS_DEBUG, "FSP MultiPhaseSiInit %s/%s called\n",
 			__FILE__, __func__);
 
-		if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS))
-			tcss_configure();
+		if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS)) {
+			const config_t *config = config_of_soc();
+			tcss_configure(config->typec_aux_bias_pads);
+		}
 		break;
 	default:
 		break;
diff --git a/src/soc/intel/tigerlake/include/soc/tcss.h b/src/soc/intel/tigerlake/include/soc/tcss.h
new file mode 100644
index 0000000000..713528bdbb
--- /dev/null
+++ b/src/soc/intel/tigerlake/include/soc/tcss.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef _SOC_TCSS_H_
+#define _SOC_TCSS_H_
+
+/* IOM aux bias control registers in REGBAR MMIO space */
+#define IOM_AUX_BIAS_CTRL_PULLUP_OFFSET_0	0x1070
+#define IOM_AUX_BIAS_CTRL_PULLUP_OFFSET(x)	(IOM_AUX_BIAS_CTRL_PULLUP_OFFSET_0 + (x) * 4)
+#define IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET_0	0x1088
+#define IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET(x)	(IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET_0 + (x) * 4)
+
+#endif /* _SOC_TCSS_H_ */