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authorJeremy Soller <jeremy@system76.com>2021-08-12 10:49:58 -0600
committerFelix Held <felix-coreboot@felixheld.de>2021-08-24 14:50:16 +0000
commite7aa4541d432b3d543b55067dc277b77f0c18f8c (patch)
treed8e3e53f25d8efadcb2cfcc1fe4e3e572bafa6d8 /src/soc/intel/tigerlake
parentbc071feec18fb7feffbcacde74d101348c65e98e (diff)
soc/intel/tgl: Add PCR_PSF3_T0_SHDW_PMC_REG_BASE for PCH-H
Change-Id: Id5b0cfeed35d1be0dc6ca03cb0c7a2fca4277676 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/tigerlake')
-rw-r--r--src/soc/intel/tigerlake/bootblock/pch.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c
index 5cb3d630af..f613a959e2 100644
--- a/src/soc/intel/tigerlake/bootblock/pch.c
+++ b/src/soc/intel/tigerlake/bootblock/pch.c
@@ -28,7 +28,11 @@
#include <soc/pcr_ids.h>
#include <soc/pm.h>
+#if CONFIG(SOC_INTEL_TIGERLAKE_PCH_H)
+#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x1000
+#else
#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x1100
+#endif
#define PCR_PSFX_TO_SHDW_BAR0 0
#define PCR_PSFX_TO_SHDW_BAR1 0x4
#define PCR_PSFX_TO_SHDW_BAR2 0x8