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path: root/src/soc/intel/tigerlake
AgeCommit message (Expand)Author
2021-08-24soc/intel/tigerlake: Add PCH-H PMC GPE group definitionsJeremy Soller
2021-08-24soc/intel/tigerlake: Add PCH-H chipset devicetreeJeremy Soller
2021-08-24soc/intel/tigerlake: Add TGL-H power limitsJeremy Soller
2021-08-24soc/intel: Add TGL-H CPUIDJeremy Soller
2021-08-19soc/intel/common: Add TGL-H PCI IDsJeremy Soller
2021-08-16mb/*/{tglrvp,volteer,deltaur}: move cpu_cluster configuration to chipset.cbMAULIK V VAGHELA
2021-08-15soc/intel/tigerlake: Select SF_MASK_2WAYS_PER_BIT if eNEM is enableSubrata Banik
2021-08-13soc/intel/tgl: Hook up ucode for TGL-U and TGL-RTim Crawford
2021-08-12soc/intel/tigerlake: Clean up FSP chipset lockdown configurationFelix Singer
2021-08-12soc/intel/tgl: Allow setting PCIe subsystem IDs after FSP-STim Crawford
2021-08-04Move post_codes.h to commonlib/console/Ricardo Quesada
2021-08-03soc/intel/*: Allow configuring 8254 timer via CMOSSean Rhodes
2021-07-26src/*: Specify type of `CBFS_SIZE` onceAngel Pons
2021-07-19soc/intel/common: Rename kconfig PMC_EPOCLean Sheng Tan
2021-07-17soc/intel/tigerlake: Make use of `cpu/intel/cpu_ids.h'Subrata Banik
2021-07-15soc/intel/tigerlake: Use `is_devfn_enabled()` for Crashlog UPDsSubrata Banik
2021-07-02src: Introduce `ARCH_ALL_STAGES_X86`Angel Pons
2021-07-01soc/intel: Refactor `xdci_can_enable()` functionAngel Pons
2021-06-30soc/intel/tigerlake: Send End-of-Post message to CSETim Wawrzynczak
2021-06-30soc/intel/common: Move PMC EPOC related code to Intel common codeLean Sheng Tan
2021-06-30src: Move `select ARCH_X86` to platformsAngel Pons
2021-06-29soc/intel/tigerlake: Enable support for common IRQ blockTim Wawrzynczak
2021-06-28soc/intel: Drop casts around `soc_read_pmc_base()`Angel Pons
2021-06-23soc/intel/tigerlake: Use devfn_disable() function for XDCISubrata Banik
2021-06-17soc/intel/{alderlake,tigerlake}: Fix typo in pmc.hWerner Zeh
2021-06-16soc/intel/tigerlake: Make use of is_devfn_enabled() functionSubrata Banik
2021-06-14util: Add DDR4 generic SPD for MT40A512M16TB-062E:RWisley Chen
2021-06-10soc/intel/tigerlake: Move MAX_CPUS to KconfigAndy Pont
2021-06-10soc/intel/tigerlake: Hook up FSP repositoryFelix Singer
2021-06-07cpu/x86: Default to PARALLEL_MP selectedKyösti Mälkki
2021-06-07soc/intel: Drop unused lpss functionsFurquan Shaikh
2021-05-27soc/intel/tigerlake: Return TBT PowerResource from PR0 and PR3John Zhao
2021-05-26soc/intel/tigerlake: Add validity for TBT firmware authenticationJohn Zhao
2021-05-18cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=yArthur Heymans
2021-05-14soc/intel/tigerlake: Allow devicetree to fill UPD related to TCSS OCNick Vaccaro
2021-05-13src: Match array format in function declarations and definitionsPatrick Georgi
2021-05-07soc/intel/{adl,tgl,jsl}: Enable power button smi after BS_CHIPS_EXITKane Chen
2021-05-07soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmasterKane Chen
2021-05-06soc/intel/tgl,mb/google/volteer: Add API for Type-C aux bias padsTim Wawrzynczak
2021-05-06soc/intel/tigkerlake: Add IOM PCR PIDTim Wawrzynczak
2021-05-06soc/intel/tigerlake: Add known CPU Port IDs for GPIO communitiesTim Wawrzynczak
2021-05-06soc/intel/tigerlake: Add known GPIO virtual wire informationTim Wawrzynczak
2021-05-03soc/intel/*: Update data types for variables holding PCH_DEVFN_* macrosTim Wawrzynczak
2021-05-03device: Switch pci_dev_is_wake_source to take pci_devfn_tTim Wawrzynczak
2021-04-26soc/intel/tigerlake: Use device ID from pci_devs header fileJohn Zhao
2021-04-21soc/intel: Replace open-coded buffer length calculationAngel Pons
2021-04-21soc/intel: Fix typo in commentAngel Pons
2021-04-21soc/intel/alderlake: rename CONFIG_MAX_PCIE_CLOCKS to CONFIG_MAX_PCIE_CLOCK_SRCRizwan Qureshi
2021-04-21soc/intel/tigerlake: Fix devices list in the DMAR DRHD structureJohn Zhao
2021-04-13dptf: Move platform-specific information to `struct dptf_platform_info`Tim Wawrzynczak
2021-04-06intel/tigerlake: Add Acoustic featuresShaunak Saha
2021-03-28soc/intel/tigerlake: Fix REG_BASE_SIZETim Wawrzynczak
2021-03-28soc/intel/tigerlake: Move TCSS code to intel/common/blockTim Wawrzynczak
2021-03-27soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.hSubrata Banik
2021-03-22soc/intel/tigerlake: Add #include guards to soc/early_tcss.hTim Wawrzynczak
2021-03-22util: Add DDR4 generic SPD for H4AAG165WB-BCWENick Vaccaro
2021-03-19soc/intel/tgl: Add configurable value for PmcUsb2PhySusPgEnableDerek Huang
2021-03-15soc/intel/tigerlake: Remove obsolete CNVi Bluetooth PCI deviceCliff Huang
2021-03-15soc/intel/tigerlake: Add CNVi Bluetooth flag at devicetree entryCliff Huang
2021-03-12soc/intel/*: drop UART pad configuration from common codeMichael Niewöhner
2021-03-05soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during bootBrandon Breitenstein
2021-03-05soc/tigerlake: Fix TCSS code to calling back and forth to mainboard and socBrandon Breitenstein
2021-03-05soc/intel/tigerlake: Fix NULL being passed for response bufferFurquan Shaikh
2021-03-03soc/intel: Factor out common smmrelocate.cAngel Pons
2021-03-03soc/intel/tigerlake: Re-use existing define in CrashLog implementationFrancois Toguo
2021-03-03soc/intel: Retype `CnviBtAudioOffload` devicetree optionAngel Pons
2021-03-01soc/intel: Drop `bootblock_cpu_init()` functionAngel Pons
2021-03-01soc/intel: Drop `romstage_pch_init()` functionAngel Pons
2021-03-01soc/intel: Factor out common smbus.hAngel Pons
2021-03-01soc/intel: Factor out common gpe.hAngel Pons
2021-03-01soc/intel: Factor out identical acpigen GPIO helpersAngel Pons
2021-03-01soc/intel: Include gfx.asl from northbridgeAngel Pons
2021-02-24soc/intel/*/smmrelocate.c: Sync includesAngel Pons
2021-02-24soc/intel/*/smmrelocate.c: Uniformize cosmeticsAngel Pons
2021-02-24soc/intel/*/pmutil.c: Align cosmetics across platformsAngel Pons
2021-02-24soc/intel/{adl,jsl,ehl,tgl}: Remove ITSS polarity restoreAamir Bohra
2021-02-23soc/intel/tigerlake: Remove polling for Link Active Status at resumeJohn Zhao
2021-02-22soc/intel/tigerlake: Enable end of post support in FSPNick Vaccaro
2021-02-22soc/intel/tigerlake: Add CrashLog implementation for intel TGLFrancois Toguo
2021-02-16vc/google/chromeos: Always use CHROMEOS_RAMOOPS_DYNAMICKyösti Mälkki
2021-02-16ACPI: Add acpi_reset_gnvs_for_wake()Kyösti Mälkki
2021-02-16soc/intel: Drop aliases on MMCONF_BASE_ADDRESSKyösti Mälkki
2021-02-15soc/intel: Remove unused <console/console.h>Elyes HAOUAS
2021-02-11src: Remove unused <arch/cpu.h>Elyes HAOUAS
2021-02-10soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard designShreesh Chhabbi
2021-02-09soc/amd,intel: Drop s3_resume parameter on FSP-S functionsKyösti Mälkki
2021-02-08soc/intel: Drop CID1 from GNVSKyösti Mälkki
2021-02-06drivers/intel/fsp2_0: Add support for MP services2 PPIAamir Bohra
2021-02-06intel: Rename config FSP_USES_MP_SERVICES_PPI to MP_SERVICES_PPIFurquan Shaikh
2021-02-06intel: Drop FSP_PEIM_TO_PEIM_INTERFACEFurquan Shaikh
2021-02-04soc/intel/tigerlake: Drops 100ms delay in TBT PCIe root ports _PS0John Zhao
2021-02-03soc/intel/tgl: Add configurable value for ConfigTdpLevelDerek Huang
2021-02-03src: Remove unused <cbmem.h>Elyes HAOUAS
2021-01-31soc/intel/*: drop incomplete and unneeded check for DMI SRLOCKMichael Niewöhner
2021-01-30soc/intel: Replace `SA_PCIEX_LENGTH` Kconfig optionsAngel Pons
2021-01-29device/Kconfig: Declare MMCONF symbols' type onceAngel Pons
2021-01-28arch/x86: Remove most C_ENV_BOOTBLOCK_SIZE limitsKyösti Mälkki
2021-01-26soc/intel: Move c-state resource defineMarc Jones
2021-01-25soc/intel/{skl,cnl,xsp,icl,tgl,ehl,adl,jsl}: use common LPC mirroringMichael Niewöhner
2021-01-25soc/intel/tgl and tgl mb/google,intel: Use the newly added meminit block driverFurquan Shaikh