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2022-07-20soc/intel/common/pch: Decouple CLIENT from BASEAngel Pons
In preparation to add a third option, have "Client" platforms select a dedicated Kconfig option instead of the common "_BASE" option. Rewrite the help texts to clarify what "Client" and "Server" mean, because the terms refer to the type of silicon and not to the market segment. Some uniprocessor (single-socket) servers are actually client platforms and there are some multi-socket workstations based on a server platform. Change-Id: I646729d709f60ca2b5e74df18c2b4e52f9b10e6b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-06-27soc/intel/*/Kconfig: Fix typo in commentAngel Pons
clcok ---> clock Change-Id: Ie41524f6500479162984fa9050d942f4e295f00a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-06-22soc/intel/tigerlake: Replace spaces with tabsSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9b64375d905d93a8db726202ed2ce932fa536da3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-22device/resource: Add _kb postfix for resource allocatorsKyösti Mälkki
There is a lot of going back-and-forth with the KiB arguments, start the work to migrate away from this. Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-04soc/intel: Rename heci_init to cse_initSubrata Banik
This patch renames heci_init() to cse_init() as HECI initialization should have a bigger scope than just initializing the CSE (a.k.a HECI1 alone). BUG=none TEST=Able to build and boot google/taeko. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic7edd55ccdcd70b244615fa06f81803a0ae6ce80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-02soc/intel/common/cpu: Use SoC overrides to set CPU privilege levelSubrata Banik
This patch implements a SoC overrides to set CPU privilege level as the MSR is not consistent across platforms. For example: On APL/GLK/DNV, it's MSR 0x120 and CNL onwards it's MSR 0x151. BUG=b:233199592 TEST=Build and boot google/taeko to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4584516102560e6bb2a4ae8c0d036be40ed96990 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-05-28soc/intel/tgl: Add PEG devices to PCI constraintsTim Crawford
Based on the constraints for CML. Fixes the following warnings in Linux on system76/oryp8 and system76/gaze16, which have an NVIDIA GPU on the bridge. pcieport 0000:00:01.0: can't derive routing for PCI INT A pcieport 0000:00:01.0: can't derive routing for PCI INT B This, in turn, resolves an IRQ conflict with the PCH HDA device that would cause a stack trace on every boot and on S3 suspend. irq 10: nobody cared (try booting with the "irqpoll" option) <snip> [<00000000fb84c354>] azx_interrupt [snd_hda_codec] Disabling IRQ #10 Change-Id: Ibc968aaa7bf0259879097ff69d2543dcfa2e5e4b Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-26soc/intel/tigerlake: Hook up FSP hyper-threading setting to option APIFelix Singer
Select `HAVE_HYPERTHREADING` and hook up the hyper-threading setting from the FSP to the option API so that related mainboards don't have to do that. Unless otherwise configured (e.g. the CMOS setting or overriden by the mainboard code), the value from the Kconfig setting `FSP_HYPERTHREADING` is used. Also, remove related code from the mainboard starlabs/laptop/tgl, since it is obsolete now. Change-Id: I49bbd4a776b4e6c55cb373bbf88a3ca076342e3e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-05-25soc/intel/tigerlake: Drop unused `PCH_DEV_SLOT_LPC` macroSubrata Banik
This patch drops the unused `PCH_DEV_SLOT_LPC` macro from the Tiger Lake SoC PCI device list. BUG=none TEST=Able to build and boot volteer, google board. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I27a2f31aa706c4d76e9f0db202422bc129368959 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-05-16soc/intel/*: Fix up header guardsArthur Heymans
Change-Id: If9ae375629c8af3d32b4c5493b5d63203e8847aa Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-05-16soc/intel/*: Use SSDT to pass A4GB and A4GSArthur Heymans
GNVS is more fragile as you need to keep struct elements in sync with ASL code. Change-Id: I2cd5e6b56e4a0dbbb11f4a0ac97e8f84d53b90ec Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-05-16soc/inte/*/gpio; Add GPE_EN and GPE_STS register definitionMaulik V Vaghela
coreboot needs to set GPE_EN bit for the GPIOs which are wake capable from s0ix/sleep. Due to GPIO locking mechanism, coreboot/OS will not be able to write GPE_EN register post GPIO has been locked. This patch adds support in SoC code to provide correct offset for GPE_EN and GPE_STS registers to the common code. Plan is to use this offsets to set GPE_EN bits before GPIO locking in coreboot which will be part of subsequent CL. BUG=b:222375516 BRANCH=firmware-brya-14505.B TEST=Check if code compiles for Brya and correct offset values are printed. Change-Id: I6b813b30b8b360f8eccbf539b57387310e380560 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-13soc/intel/tigerlake/meminit.c: Fix clang static assertsArthur Heymans
Clang does not like static asserts on integral constant expressions. Change-Id: If5890a357ed95153d8ae2efa727c111b05bc6455 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-05soc/intel/tigerlake: Add enum for `DdiPortXConfig`Angel Pons
Add an enum for `DdiPortXConfig` devicetree options. Note that setting these options to zero does not disable the corresponding DDI port, but instead indicates that no LFP (Local Flat Panel, i.e. internal LCD) is connected to it. Change-Id: I9ea10141e51bf29ea44199dcd1b55b63ec771c0a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2022-04-29soc/{amd/stoneyridge,intel}: Don't select VBOOT_SEPARATE_VERSTAGEArthur Heymans
Now the bootblock is not limited to 64K so integrating vboot into the bootblock reduces the binary size. intel/apl is an exception since the bootblock size is limited to 32K. Change-Id: I5e02961183b5bcc37365458a3b10342e5bc2b525 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-29soc/intel: Decouple HECI disabling interface from HECI disable KconfigSubrata Banik
This patch decouples HECI disabling interface a.k.a SMM or PCR or PMC IPC etc. from DISABLE_HECI1_AT_PRE_BOOT kconfig as Intel ME BWG recommends to disable the CSE PCI device while CSE is in software temporary disable state. BUG=b:228789015 TEST=Able to build google/redrix. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I66abc04d5e195515165a77b0166d004f17d029e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-04-27soc/intel/cmn/lockdown: Perform SA lockdown configurationSubrata Banik
`sa_lockdown_cfg` function ensures locking the PAM register hence, skip dedicated calling into `sa_lock_pam()` from the SoC `finalize.c` file. Dropped sa_lock_pam() call from ADL/CNL/EHL/JSL and TGL. Additionally, this patch enforces SA lockdown configuration for SKL and ICL as well. BUG=b:211954778 TEST=Able to build google/brya with these changes. > localhost ~ # lspci -xxx | less 00:00.0 Host bridge: Device 8086:4601 (rev 04) Bit 0 for all PAM registers a.k.a, PAMx_0_0_0_PCI.LOCK bit is set (meaning locked). Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ibd464d2507393ed0c746eb1fbd10e36092ed5599 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-22soc/intel: Remove unused <cbmem.h>Elyes HAOUAS
Change-Id: I529c822c9e952dae6613d3de64f6709e0fd9b385 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-21tpm: Refactor TPM Kconfig dimensionsJes B. Klinke
Break TPM related Kconfig into the following dimensions: TPM transport support: config CRB_TPM config I2C_TPM config SPI_TPM config MEMORY_MAPPED_TPM (new) TPM brand, not defining any of these is valid, and result in "generic" support: config TPM_ATMEL (new) config TPM_GOOGLE (new) config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE) config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE) What protocol the TPM chip supports: config MAINBOARD_HAS_TPM1 config MAINBOARD_HAS_TPM2 What the user chooses to compile (restricted by the above): config NO_TPM config TPM1 config TPM2 The following Kconfigs will be replaced as indicated: config TPM_CR50 -> TPM_GOOGLE config MAINBOARD_HAS_CRB_TPM -> CRB_TPM config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE Signed-off-by: Jes B. Klinke <jbk@chromium.org> Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-20soc/intel: clean up dmi driver codeWonkyu Kim
1. Remove dmi.h as it's migrated as gpmr.header 2. Remove unused gpmr definitions 3. For old platforms, define DMI defintions in c code for less code changes. TEST=Build Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ib340ff1ab7fd88b1e7b3860ffec055a75e562de7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-04-06soc/intel/(cnl, jsl, tgl): Enable SOC_INTEL_COMMON_BASECODESridhar Siricilla
The patch SOC_INTEL_COMMON_BASECODE Kconfig for Comet Lake, Jasper Lake and Tiger Lake SoCs. It allows access to intelbasecode/debug_feature.h for Comet Lake, Jasper Lake and Tiger Lake SoCs. TEST=Build code for Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ie55ded673c8fa0edf2ca6789b15771bd2e56c95e Reviewed-on: https://review.coreboot.org/c/coreboot/+/62843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-06soc/intel/common: Abstract the common TCSS functionsJohn
This change abstracts the common TCSS functions for pad configuration and Thunderbolt authentication. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Change-Id: I3302aabfb5f540c41da6359f11376b4202c6310b Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-29soc/intel: Move `pmc_clear_pmcon_sts()` into IA common codeSubrata Banik
This patch moves `pmc_clear_pmcon_sts` function into common code and remove SoC specific instances. Accessing PMC GEN_PMCON_A register differs between different Intel chipsets. Typically, there are two possible ways to perform GEN_PMCON_A register programming (like `pmc_clear_pmcon_sts()`) as: 1. Using PCI configuration space when GEN_PMCON_A is a PCI configuration register. 2. Using MMIO access when GEN_PMCON_A is a memory mapped register. SoC users to select `SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION` Kconfig to perform GEN_PMCON_A register programming using PMC MMIO. BUG=b:211954778 TEST=Able to build brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8d15f421c128630f928a1b6a7e2840056d68d7b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeff Daly <jeffd@silicom-usa.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-03-15soc/intel/tgl: move DIMM_SPD_SIZE from mb to SoC KconfigMichael Niewöhner
All TGL mainboards are setting DIMM_SPD_SIZE to 512. Thus, default to 512 in the SoC Kconfig and drop it from the mainboard Kconfigs. Change-Id: I9fd947b61c984e10bd5fba20b73280b08623a008 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62766 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-15{mb, soc}: Move mrc_cache invalidating logic into `memory` common codeSubrata Banik
Commit hash b8b40964 ( mb, soc: Add the SPD_CACHE_ENABLE) introduced per mainboard logic to invalidate the mrc_cache. This patch moves mrc_cache invalidating logic into IA common code and cleans up the code to remove unused argument `dimms_changed` from SoC and mainboard directory. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=Able to build and boot redrix without any visible failure/errors. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6f18e18adc6572571871dd6da1698186e4e3d671 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-15soc/intel/common: Pass `FSPM_UPD *` argument for spd functionsSubrata Banik
This patch adds `FSPM_UPD *` as argument for mem_populate_channel_data() and read_spd_dimm(). This change will help to update the architectural FSP-M UPDs in read_spd_dimm(). BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=Able to build and boot redrix without any visible failure/errors. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I770cfd05194c33e11f98f95c5b93157b0ead70c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-15{mb, soc}: Change `memcfg_init()` and `variant_memory_init()` prototypeSubrata Banik
This patch modifies `memcfg_init` and `variant_memory_init`functions argument from FSP_M_CONFIG to FSPM_UPD. This change in `memcfg_init()` argument will help to update the architectural FSP-M UPDs from common code blocks rather than going into SoC and/or mainboard implementation. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=Able to build and boot redrix without any visible failure/errors. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3002dd5c2f3703de41f38512976296f63e54d0c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-08soc/intel/tgl: chipset devicetree: correct TraceHub device aliasMichael Niewöhner
Device 1f.7 is TraceHub, not the PCH Thermal device, which doesn't exist anymore on TGL. Correct the device´s alias. Reference: Intel doc# 631119-007 Change-Id: I30a4ab1e801f6cdb0f2e03f105bf8cc09592eed8 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-08soc/intel/tgl: drop orphaned VR domains enumMichael Niewöhner
Change-Id: I937bdf032e1ed86900334d41655f3e6272f66a6f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-07soc/intel/tigerlake: Hide PMC and IOM devicesMichał Kopeć
Windows complains on missing drivers for these ACPI devices. Hide them from OS as it doesn't influence the hardware operation. Linux can still probe the drivers correctly. TEST=Boot Windows 11 and see there are no devices with missing drivers. Boot Ubuntu 20.04 and check that drivers corresponding to ACPI HIDs are still probed. Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Change-Id: I6c30c08ab730749bddef7ea67c7470c1554bd572 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-07src: Make PCI ID define names shorterFelix Singer
Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with PCI_{DID,VID}_ using the commands below, which also take care of some spacing issues. An additional clean up of pci_ids.h is done in CB:61531. Used commands: * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g' * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g' Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-03-02mb, soc: Add the SPD_CACHE_ENABLEZhuohao Lee
In order to cache the spd data which reads from the memory module, we add SPD_CACHE_ENABLE option to enable the cache for the spd data. If this option is enabled, the RW_SPD_CACHE region needs to be added to the flash layout for caching the data. Since the user may remove the memory module after the bios caching the data, we need to add the invalidate flag to invalidate the mrc cache. Otherwise, the bios will use the mrc cache and can make the device malfunction. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=build pass and enable this feature to the brask the device could speed up around 150ms with this feature. Change-Id: If7625a00c865dc268e2a22efd71b34b40c40877b Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62294 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25intelblocks/pcie: Correct mapping between LCAP port and coreboot indexMAULIK V VAGHELA
coreboot uses port index which is 0 based for all PCIe root ports. In case of PCIe remapping logic, coreboot reads LCAP register from PCIe configuration space which contains port number (mostly 1 based). This assumption might not be true for all the ports in coreboot. TBT's LCAP registers are returning port index which are based on 2. coreboot's PCIe remapping logic returns port index based on index 1. This patch adds variable to pcie_rp_config to pass lcap_port_base to the pcie remapping function, so coreboot can map any n-based LCAP encoding to 0-based indexing scheme. This patch updates correct lcap_port_base variable for all PCIe root ports for all SOCs, so that function returns correct 0-based index from LCAP port number. BUG=b:210933428 BRANCH=None TEST=Check if code compiles for all ADL boards Change-Id: I7f9c3c8e753b982e2ede1a41bf87d6355b82da0f Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61936 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25arch/x86: factor out and commonize HPET_BASE_ADDRESS definitionFelix Held
All x86 chipsets and SoCs have the HPET MMIO base address at 0xfed00000, so define this once in arch/x86 and include this wherever needed. The old AMD AGESA code in vendorcode that has its own definition is left unchanged, but sb/amd/cimx/sb800/cfg.c is changed to use the new common definition. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifc624051cc6c0f125fa154e826cfbeaf41b4de83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-02-18drivers/fsp/fsp2_0: Rework FSP Notify Phase API configsSubrata Banik
This patch renames all FSP Notify Phase API configs to primarily remove "SKIP_" prefix. 1. SKIP_FSP_NOTIFY_PHASE_AFTER_PCI_ENUM -> USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM 2. SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT -> USE_FSP_NOTIFY_PHASE_READY_TO_BOOT 3. SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE -> USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE The idea here is to let SoC selects all required FSP configs to execute FSP Notify Phase APIs unless SoC deselects those configs to run native coreboot implementation as part of the `.final` ops. For now all SoC that uses FSP APIs have selected all required configs to let FSP to execute Notify Phase APIs. Note: coreboot native implementation to skip FSP notify phase API (post pci enumeration) is still WIP. Additionally, fixed SoC configs inclusion order alphabetically.  BUG=b:211954778 TEST=Able to build and boot brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib95368872acfa3c49dad4eb7d0d73fca04b4a1fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/61792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-15soc/intel/*/pmc: Add `finalize` operation for pmcSubrata Banik
This patch implements the required operations to perform prior to booting to OS using coreboot native driver when platform decides to skip FSP notify APIs, i.e., Ready to Boot and End Of Firmware. Additionally, move the PMCON status bit clear operation to `.final` ops to cover any such chances where FSP-S Notify Phase or any other later boot stage may request a global reset and PMCON status bit remains set. BUG=b:211954778 TEST=Able to build brya with these changes. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0a0b869849d5d8c76031b8999f3d28817ac69247 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-02-07treewide: Remove "ERROR: "/"WARN: " prefixes from log messagesJulius Werner
Now that the console system itself will clearly differentiate loglevels, it is no longer necessary to explicitly add "ERROR: " in front of every BIOS_ERR message to help it stand out more (and allow automated tooling to grep for it). Removing all these extra .rodata characters should save us a nice little amount of binary size. This patch was created by running find src/ -type f -exec perl -0777 -pi -e 's/printk\(\s*BIOS_ERR,\s*"ERROR: /printk\(BIOS_ERR, "/gi' '{}' ';' and doing some cursory review/cleanup on the result. Then doing the same thing for BIOS_WARN with 's/printk\(\s*BIOS_WARNING,\s*"WARN(ING)?: /printk\(BIOS_WARNING, "/gi' Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I3d0573acb23d2df53db6813cb1a5fc31b5357db8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Lance Zhao Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-02-05cpu/x86/lapic: Move LAPIC configuration to MP initKyösti Mälkki
Implementation for setup_lapic() did two things -- call enable_lapic() and virtual_wire_mode_init(). In PARALLEL_MP case enable_lapic() was redundant as it was already executed prior to initialize_cpu() call. For the !PARALLEL_MP case enable_lapic() is added to AP CPUs. Change-Id: I5caf94315776a499e9cf8f007251b61f51292dc5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-02soc/intel/tigerlake: Use PMC IPC to disable HECI1Subrata Banik
This patch allows common CSE block to disable HECI1 device using PMC IPC command `0xA9`. Select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC config for Tiger Lake to disable HECI1 device using PMC IPC. Additionally, remove dead code that deals with HECI1 disabling using in SMM as HECI1 disabling using PMC IPC is simpler solution. BUG=none TEST=None Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Id5f1e3f622f65cd0f892c0dc541625bfd50d038e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-02soc/intel/common/cse: Rework heci_disable functionSubrata Banik
This patch provides the possible options for SoC users to choose the applicable interface to make HECI1 function disable at pre-boot. `SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_SBI` config is used for disabling heci1 using non-posted sideband write (inside SMM) after FSP-S sets the postboot_sai attribute. Applicable from CNL PCH onwards. `SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PMC_IPC` config is used for disabling heci1 using PMC IPC command `0xA9`. Applicable from TGL PCH onwards. `SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PCR` config is used for disabling heci1 using private configuration register (PCR) write. Applicable for SoC platform prior to CNL PCH. Additionally, add PID_CSME0 macro for SKL, Xeon_SP and APL to fix the compilation failure. Finally, rename heci_disable() function to heci1_disable() to make it more meaningful. BUG=none TEST=Able to build and boot brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7e0bab0004013b999ec1e054310763427d7b9348 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-28soc/intel: Abstract the common block API for TCSS registers accessJohn Zhao
The existing TCSS registers access is through the REGBAR. There will be future platforms which access the TCSS registers through the Sideband interface. This change abstracts the common block API for TCSS access. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I3e2696b117af24412d73b257f470efc40caa5022 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-19soc/intel/common/cpu: Use SoC overrides to get CPU privilege levelSubrata Banik
This patch implements a SoC overrides to check CPU privilege level as the MSR is not consistent across platforms. For example: On APL/GLK/DNV, it's MSR 0x120 and CNL onwards it's MSR 0x151. BUG=b:211573253, b:211950520 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I515f0a3548bc5d6250e30f963d46f28f3c1b90b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-14soc/intel/tgl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik
List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4a81fd58df468e2711108a3243bf116e02986316 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-14soc/intel/tigerlake: add devicetree option PcieRpSlotImplementedMichael Niewöhner
Add the UPD PcieRpSlotImplemented as devicetree option. To keep the PI bit set for any slots of already existing boards, add set the option PcieRpSlotImplemented=1 where appropriate. Change-Id: Ia6f685df3c22c74ae764693329a69817bf3cd01d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-14soc/intel/tgl: deduplicate the PCIe root port mapMichael Niewöhner
Make use of the helper introduced in the parent change to deduplicate the PCIe root port table. Change-Id: I2dae4e4caf0a7ba3662889f3b31da0c3c299bc92 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-14soc/intel/tgl/pcie_rp: add TGL-H supportMichael Niewöhner
Add TGL-H support for the recently introduced code for differentiating CPU and PCH root ports by adding the missing TGL-H port map. Change-Id: Id2911cddeb97d6c164662e2bef4fdeece10332a8 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-01-12soc/intel/tigerlake: Implement function to map physical port to EC portjzhao80
Currently coreboot and EC had different logic to interpret TCSS port number which would break retimer update functionality since coreboot would pass wrong port information to EC. This change clones the implementation on Alder Lake which converts the phyiscal port mapping to EC's abstract port mapping. BUG=b:207057940 BRANCH=None Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: If4451598dbb83528ae6d88dbc1b65c206f24fe1f Reviewed-on: https://review.coreboot.org/c/coreboot/+/60972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-12soc/intel/tgl/pcie_rp: correct root port mapMichael Niewöhner
TGL-LP only has 12 root ports, not 20. Correct the port map. Change-Id: I3f5c69a2e7e3a2b8292c81beeac4ea6c7279d4b4 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-01-10src/soc/intel: Remove unused <console/console.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<" Change-Id: I2ca3a7487cbe75f9bec458f4166378a07b833bb5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-09soc/intel/{icl,tgl,jsl,ehl}: enable ACPI CPPC entriesMichael Niewöhner
Enable CPPC entries generation, needed for Intel SpeedShift. This can be tested by checking sysfs in Linux: $ grep . /sys/devices/system/cpu/cpu?/acpi_cppc/*perf The output should look like this, while the values may differ: /sys/devices/system/cpu/cpu0/acpi_cppc/highest_perf:28 /sys/devices/system/cpu/cpu0/acpi_cppc/lowest_nonlinear_perf:5 /sys/devices/system/cpu/cpu0/acpi_cppc/lowest_perf:1 /sys/devices/system/cpu/cpu0/acpi_cppc/nominal_perf:24 /sys/devices/system/cpu/cpu1/acpi_cppc/highest_perf:28 /sys/devices/system/cpu/cpu1/acpi_cppc/lowest_nonlinear_perf:5 ... Change-Id: I910b4e17d4044f1bf1ecfa0643ac62fc7a8cb51b Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
2022-01-06soc/intel/tigerlake: Add soc_get_cpu_rp_vw_idx() functionTim Wawrzynczak
The PMC IPC method used to enable/disable PCIe clk sources uses the LCAP PN field to distinguish PCH RPs. For CPU RPs, the PMC IPC command expects the RP number to be its "virtual wire index" instead. This new function returns this virtual wire index for each of the CPU PCIe RPs. BUG=b:197983574 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I7aa14a634dcd90c4817009db970fb209ae02c63d Reviewed-on: https://review.coreboot.org/c/coreboot/+/60179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-01-05src/soc/intel: Remove unused <delay.h>Elyes HAOUAS
Change-Id: Id8e6221a9801d5198171dc9cd564000d19720a42 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-05soc/intel: Remove unused <string.h>Elyes HAOUAS
Found using following command: diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy(\|memmove(\|memset(\|memcmp(\|memchr(\|strdup(\|strconcat(\|strnlen(\|strlen(\|strchr(\|strncpy(\|strcpy(\|strcmp(\|strncmp(\|strspn(\|strcspn(\|strstr(\|strtok_r(\|strtok(\|atol(\|strrchr(\|skip_atoi(\|vsnprintf(\|snprintf(' -- src/) Change-Id: Iae90ff482f534d8de2a519619c20a019d054e700 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-02soc/intel/{adl,ehl,tgl}: Rename spi_protection_mode to mfg_modeSubrata Banik
Since TGL `spi_protection_mode` bit replaces the previous `manufacturing mode` without changing the offset and purpose of this bit. This patch renames to `manufacturing mode` aka `mfg_mode` to maintain the parity with other PCHs as part of IA-common code. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6d00f72ce7b3951120778733066c351986ccf343 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-01soc/intel/tigerlake/fsp_params.c: Use `is_dev_enabled()`Felix Singer
Change-Id: I3e79f637bedec0bdca1312291328b2385bd027a7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-01-01src: Drop duplicated includesElyes HAOUAS
<types.h> already provides <commonlib/bsd/cb_err.h>, <limits.h>, <stdbool.h>, <stdint.h> and <stddef.h> headers. Change-Id: I700b3f0e864ecce3f8b3b66f3bf6c8f1040acee1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-12-20soc/intel/common: Do not trigger crashlog on all resets by defaultCurtis Chen
Crashlog has error records and PMC reset records two parts. When we send ipc cmd "PMC_IPC_CMD_ID_CRASHLOG_ON_RESET", PMC reset record is enabled. At each warm/cold/global reset, crashlog would be triggered. The cause of this crash would be "TRIGGER_ON_ALL_RESETS", it is used to catch unknown reset reason. At the same time, we would see [Hardware Error] in the kernel log. If we default enable TRIGGER_ON_ALL_RESETS, we would have too many false alarm. Now we disable PMC reset records part by default. And we could enable it when we need it for the debug purpose. The generated bert dump is under /var/spool/crash/, we could check this path to verify this CONFIG disable/enable status. BUG=b:202737385 TEST=No new bert dump after a warm reset. Signed-off-by: Curtis Chen <curtis.chen@intel.com> Change-Id: I3ec4ff3c8a3799156de030f4556fe6ce61305139 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-13soc/intel/tigerlake: Define soc_get_pcie_rp_typeTim Wawrzynczak
In order to distinguish PCH from CPU PCIe RPs, define the soc_get_pcie_rp_type function for Tiger Lake. BUG=b:197983574 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ic3f7d3f2fc12ae2b53604cd8f8b694a7674c3620 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-12-09soc/intel/tigerlake: Hook up DPTF device to devicetreeFelix Singer
Hook up `Device4Enable` FSP setting to devicetree state and drop its redundant devicetree setting `Device4Enable`. The following mainboards enable the DPTF device in the devicetree despite `Device4Enable` is not being set. * google/deltaur Thus, set it to off to keep the current state unchanged. Change-Id: Ic7636fc4f63d4beab92e742a6882ac55af2565bc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-09soc/intel/tigerlake: Drop unused SataEnable settingFelix Singer
`SataEnable` is set by some boards, but it doesn't have any effect since its related FSP option is hooked up to the devicetree state. Thus, drop it. Change-Id: Id645bfcade7ca1d495fb8df538113b3d10392a82 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-09soc/intel/tigerlake: Hook up SMBus device to devicetreeFelix Singer
Hook up `SmbusEnable` FSP setting to devicetree state and drop its redundant devicetree setting `SmbusEnable`. The following mainboards enable the SMBus device in the devicetree despite `SmbusEnable` is not being set. * google/deltaur * starlabs/laptop Thus, set it to off to keep the current state unchanged. Change-Id: I0789af20beb147fc1a6a7d046cdcea15cb44ce4c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-22soc/intel/{adl,ehl,jsl,tgl}: Remove unused header `thermal.h`Subrata Banik
This patch removes unused header inclusion as <intelblocks/thermal.h> from several SoC finalize.c files. Change-Id: Ic9ac0ffb352686af22cc9d11b61f904238eef278 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-11-15soc/intel/tigerlake: Add config option for S3 ACPISean Rhodes
Add Kconfig option `SOC_INTEL_TIGERLAKE_S3` which will adjust the ACPI to not offer D3Cold when using S3. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ieb1cc3d6a03cb452ff38ae393a993e881d9b5ff4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-15soc/intel/tigerlake/apci: Only use SCM for ChromeOSSean Rhodes
Software Connection Manager doesn't work with Linux 5.13 or later and results in TBT ports timing out. Not advertising this results in Firmware Connection Manager being used and TBT works correctly. Linux patch: https://github.com/torvalds/linux/commit/c6da62a219d028de10f2e22e93a34c7ee2b88d03 Tested on: * StarBook Mk V * System76 Oryx Pro 8 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib947c3c9cd843e54d4664509c15336178c0bc99e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2021-11-10Rename ECAM-specific MMCONF KconfigsShelley Chen
Currently, the MMCONF Kconfigs only support the Enhanced Configuration Access mechanism (ECAM) method for accessing the PCI config address space. Some platforms have a different way of mapping the PCI config space to memory. This patch renames the following configs to make it clear that these configs are ECAM-specific: - NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT - MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT - MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS - MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER - MMCONF_LENGTH --> ECAM_MMCONF_LENGTH Please refer to CB:57861 "Proposed coreboot Changes" for more details. BUG=b:181098581 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max Make sure Jenkins verifies that builds on other boards Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-08soc/intel: drop Kconfig `PM_ACPI_TIMER_OPTIONAL`Michael Niewöhner
Technically, it's not depending on the hardware but on the software (OS/payload), if the PM Timer is optional. OSes with ACPI >= 5.0A support disabling of the PM Timer, when the respective FADT flag is unset. Thus, drop this guard. For platforms without hardware PM Timer (Apollo Lake, Gemini Lake) the Kconfig `USE_PM_ACPI_TIMER` depends on `!NO_PM_ACPI_TIMER`. As of this change, new platforms must either implement code for disabling the hardware PM timer or select `NO_PM_ACPI_TIMER` if no such is present. Change-Id: I973ad418ba43cbd80b023abf94d3548edc53a561 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lance Zhao
2021-10-26soc/intel: Update api name for getting spi destination idWonkyu Kim
Update api name and comments to be more generic as spi destination id is not DMI specific. Update api name as soc_get_spi_psf_destination_id and comments. And move PSF definition from pcr_ids.h as it's not pcr id. Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ie338d05649d23bddae5355dc6ce8440dfb183073 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2021-10-26cpu/x86: Introduce and use `CPU_X86_LAPIC`Felix Held
With using a Kconfig option to add the x86 LAPIC support code to the build, there's no need for adding the corresponding directory to subdirs in the CPU/SoC Makefile. Comparing which CPU/SoC Makefiles added (cpu/)x86/mtrr and (cpu/)x86/lapic before this and the corresponding MTRR code selection patch and having verified that all platforms added the MTRR code on that patch shows that soc/example/min86 and soc/intel/quark are the only platforms that don't end up selecting the LAPIC code. So for now the default value of CPU_X86_LAPIC is chosen as y which gets overridden to n in the Kconfig of the two SoCs mentioned above. Change-Id: I6f683ea7ba92c91117017ebc6ad063ec54902b0a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-25cpu,soc/x86: always include cpu/x86/mtrr on x86 CPUs/SoCsFelix Held
All x86-based CPUs and SoCs in the coreboot tree end up including the Makefile in cpu/x86/mtrr, so include this directly in the Makefile in cpu/x86 to add it for all x86 CPUs/SoCs. In the unlikely case that a new x86 CPU/SoC will be added, a CPU_X86_MTRR Kconfig option that is selected be default could be added and the new CPU/SoC without MTRR support can override this option that then will be used in the Makefile to guard adding the Makefile from the cpu/x86/mtrr sub-directory. In cpu/intel all models except model 2065X and 206AX are selcted by a socket and rely on the socket's Makefile.inc to add x86/mtrr to the subdirs, so those models don't add x86/mtrr themselves. The Intel Broadwell SoC selects CPU_INTEL_HASWELL and which added x86/mtrr to the subdirs. The Intel Xeon SP SoC directory contains two sub-folders for different versions or generations which both add x86/mtrr to the subdirs in their Makefiles. Change-Id: I743eaac99a85a5c712241ba48a320243c5a51f76 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-22arch/x86/ioapic: Select IOAPIC with SMPKyösti Mälkki
For coreboot proper, I/O APIC programming is not really required, except for the APIC ID field. We generally do not guard the related set_ioapic_id() or setup_ioapic() calls with CONFIG(IOAPIC). In practice it's something one cannot leave unselected, but maintain the Kconfig for the time being. Change-Id: I6e83efafcf6e81d1dfd433fab1e89024d984cc1f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-22cpu/x86/mp_init: move printing of failure message into mp_init_with_smmFelix Held
Each CPU/SoC checks the return value of the mp_init_with_smm and prints the same error message if it wasn't successful, so move this check and printk to mp_init_with_smm. For this the original mp_init_with_smm function gets renamed to do_mp_init_with_smm and a new mp_init_with_smm function is created which then calls do_mp_init_with_smm, prints the error if it didn't return CB_SUCCESS and passes the return value of do_mp_init_with_smm to its caller. Since no CPU/SoC code handles a mp_init_with_smm failure apart from printing a message, also add a comment at the mp_init_with_smm call sites that the code might want to handle a failure. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I181602723c204f3e43eb43302921adf7a88c81ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/58498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-21cpu/x86/mp_init: use cb_err as mp_init_with_smm return typeFelix Held
Using cb_err as return type clarifies the meaning of the different return values. This patch also adds the types.h include that provides the definition of the cb_err enum and checks the return value of mp_init_with_smm against the enum values instead of either checking if it's non-zero or less than zero to handle the error case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibcd4a9a63cc87fe176ba885ced0f00832587d492 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19soc/intel: Constify `soc_get_cstate_map()`Angel Pons
Return a read-only pointer from the `soc_get_cstate_map()` function. Also, constify the actual data where applicable. Change-Id: I7d46f1e373971c789eaf1eb582e9aa2d3f661785 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-19soc/intel/*/acpi.c: Don't copy structs with `memcpy()`Angel Pons
A regular assignment works just as well and also allows type-checking. Change-Id: Id772771f000ba3bad5d4af05f5651c0f0ee43d6d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-18intel/tigerlake: Add missing IRQ for CNViSean Rhodes
Add CNVi (14.3) to IRQ Table to stop dmesg error: iwlwifi 0000:00:14.3: can't derive routing for PCI INT F iwlwifi 0000:00:14.3: PCI INT F: not connected Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I5b793997f9ea954217871eb4656dacf6abe77e74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-17soc/intel: transition full control over PM Timer from FSP to corebootMichael Niewöhner
Set `EnableTcoTimer=1` in order to keep FSP from 1) enabling ACPI Timer emulation in uCode. 2) disabling the PM ACPI Timer. Both actions are now done in coreboot. `EnableTcoTimer=1` makes FSP skip these steps in any possible case including `SkipMpInit=0`, `SkipMpInit=1`, use of the MP PPI or FSP Multiphase Init. This way full control is left to coreboot. Change-Id: I8005daed732c031980ccc379375ff5b09df8dac1 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lance Zhao
2021-10-17soc/intel: implement ACPI timer disabling per SoC and drop common codeMichael Niewöhner
Since it's just a one-liner, implement disabling of the ACPI timer in soc code. This reduces complexity. Change-Id: I434ea87d00f6e919983d9229f79d4adb352fbf27 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-17soc/intel: move disabling of PM Timer to SoC PMC codeMichael Niewöhner
Move disabling of PM Timer to SoC PMC code. The original reason for placing that in `finalize` [1] was FSP hanging due to use of the PM timer without enabling timer emulation first in coreboot, which was added later [2]. [1] commit 6c1bf27dae (intel/skylake: disable ACPI PM Timer to enable XTAL OSC shutdown) [2] commit f004f66ca7 (soc/intel/skylake: Enable ACPI PM timer emulation on all CPUs) Change-Id: I354c3aea0c8c1f8ff3d698e0636932b7b76125f7 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-17soc/intel: deduplicate acpi_fill_soc_wakeMichael Niewöhner
The PM1_EN bits WAK_STS, RTC_EN, PWRBTN_EN don't need any SoC-specific handling. Deduplicate `acpi_fill_soc_wake` by setting these bits in common code. Change-Id: I06628aeb5b82b30142a383b87c82a1e22a073ef5 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-12soc/intel: replace dt option PmTimerDisabled by KconfigMichael Niewöhner
Replace the dt option `PmTimerDisabled` with use of the Kconfig option `USE_PM_ACPI_TIMER` for enabling/disabling the PM Timer. A default value representing the prior devicetree value was added to the boards system76/{lemp10,galp5,darp7}, so this change will not alter behaviour. Change-Id: If1811c6b98847b22272acfa35ca44f4fbca68947 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-12soc/intel/*/cpu.c: Add missing space in commentAngel Pons
Add a space before the `*/` C-style comment ending. Change-Id: Ic8928286c8237808b9e380e4393078792589615d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-10-11soc/intel/tigerlake: Add ACPI addition for USB4/TBT latency optimizationJohn Zhao
The PCI-SIG engineering change requirement provides the ACPI additions for firmware latency optimization. This change adds additional ACPI DSM function with both of FW_RESET_TIME and FW_D3HOT_TO_D0_TIME to the USB4/TBT topology. The OS is informed to reduce latency for upstream ports while connecting USB4/TBT devices. BUG=b:199757442 TEST=It was validated that the first connected device waits only 50ms instead of 100ms and all functions work on Voxel board. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I5a19118b75ed0a78b7436f2f90295c03928300d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-07soc/intel/tigerlake: Hook up GMA ACPI brightness controlsTim Crawford
Add function needed to generate ACPI backlight control SSDT, along with Kconfig values for accessing the registers. Tested by adding gfx register on system76/gaze16 and booting Windows. Display settings has a brightness setting, and can change the brightness level. Change-Id: Id8b14c0b4a7a681dc6cb95778c12a006a7e31373 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-05src/soc to src/superio: Fix spelling errorsMartin Roth
These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58082 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-01soc/tigerlake: Make IO decode / enable register configurableSean Rhodes
This allows the one 32bit register to be configured in the devicetree in the same way that Skylake can be. i.e. register "lpc_ioe". Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib1a7f2707e565a5651ebe438320de9597f5742c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-09-29soc/intel: Drop unnecessary `select REG_SCRIPT`Angel Pons
These platforms no longer use reg-script. Drop unneeded select. Change-Id: I8fc4dc29d25dffbf9ed1947d0ff013b2fae0faaf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-29soc/intel/{cnl,jsl,tgl,ehl,adl}: rename PMC device init/enable callbacksMichael Niewöhner
The current names of the PMC init/enable callbacks are very confusing. Rename them. Change-Id: I69f54f3b4e1ea9a9b4fa5c8dd9c0d454d7cd1283 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-23soc/intel/tgl: correct wrong gpio GPI enable register base offsetMichael Niewöhner
Reference: Intel doc# 631120-001. Change-Id: Iaf3a1b7bc38a1b30f8cc901bd6496e77f2d92cfd Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-23soc/intel/{xeon-sp,icl,tgl,jsl,ehl}: add NMI_{EN,STS} registersMichael Niewöhner
Add NMI_EN and NMI_STS registers, so NMI interrupts can be used. References: - XEON-SP: Intel doc# 633935-005 and 547817 rev1.5 - ICL-LP: Intel doc# 341081-002 - TGL-LP: Intel doc# 631120-001 - TGL-H: Intel doc# 636174-002 - JSL: Intel doc# 634545-001 - EHL: Intel doc# 636722-002 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I2621f4495dfd4f95f9774d9081e44c604de830a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lance Zhao
2021-09-23mb/google/volteer: Migrate volteer to use SPD files under spd/Reka Norman
SPD files are being moved from the soc and mainboard directories to a centralised spd/ directory. This change migrates all volteer variants to use this new location. The contents of the new SPDs are identical, only their file paths have changed. The variant Makefile.inc and dram_id.generated.txt files were generated using the part_id_gen tool. E.g. for voema: util/spd_tools/bin/part_id_gen \ TGL \ lp4x \ src/mainboard/google/volteer/variants/voema/memory \ src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt BUG=b:191776301 TEST=Check that each variant's coreboot.rom is the same with and without this change. Built using: abuild -p none -t google/volteer -a -x --timeless Change-Id: Ibd4f42fd421bfa58354b532fe7a67ee59dac5e1d Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-20soc/intel/tigerlake: Clear RTC_BATTERY_DEADTim Wawrzynczak
Normally for vboot-enabled x86 board, the VBNV region is stored in CMOS and backed up to flash (RW_NVRAM). However, on the very first boot after a flash of the full SPI image (so RW_NVRAM is empty), if RTC_BATTERY_DEAD is set, coreboot persistently requests recovery before FSP-M finishes (which appears to be the current location that RTC_BATTERY_DEAD is cleared on this platform). This is because vbnv_cmos_failed() will still return 1. Therefore, immediately after reading RTC_BATTERY_DEAD, it is cleared. This prevents an infinite boot loop when trying to set the recovery mode bit. Note that this was the behavior for previous generations of Intel PMC programming as well (see southbridge/intel, soc/skylake, soc/broadwell, etc). BUG=b:181678769 Change-Id: Ie86822f22aa5899a7e446398370424ca5a4ca43d Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-20soc/intel/{common,tgl,adl}: guard TME Kconfig option by SoC supportMichael Niewöhner
Currently, Intel TME (Total Memory Encryption) can be enabled regardless of SoC support. Add a Kconfig to guard the option depending on actual support. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Ia20152bb0fc56b0aec3019c592dd6d484829aefe Reviewed-on: https://review.coreboot.org/c/coreboot/+/57762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-16drivers/intel/fsp2_0: Refactor MultiPhaseSiInit API calling methodSubrata Banik
FspMultiPhaseSiInit API was introduced with FSP 2.2 specification onwards. EnableMultiPhaseSiliconInit is an arch UPD also introduced as part of FSP 2.2 specification to allow calling FspMultiPhaseSiInit API. However, some platforms adhere to the FSP specification but don't have arch UPD structure, for example : JSL, TGL and Xeon-SP. Out of these platforms, TGL supports calling of FspMultiPhaseSiInit API and considered EnableMultiPhaseSiliconInit as a platform-specific UPD rather than an arch UPD to allow calling into FspMultiPhaseSiInit API. It is important to ensure that the UPD setting and the callback for MultiPhaseInit are kept in sync, else it could result in broken behavior e.g. a hang is seen in FSP if EnableMultiPhaseSiliconInit UPD is set to 1 but the FspMultiPhaseSiInit API call is skipped. This patch provides an option for users to choose to bypass calling into MultiPhaseSiInit API and ensures the EnableMultiPhaseSiliconInit UPD is set to its default state as `disable` so that FSP-S don't consider MultiPhaseSiInit API is a mandatory entry point prior to calling other FSP API entry points. List of changes: 1. Add `FSPS_HAS_ARCH_UPD` Kconfig for SoC to select if `FSPS_ARCH_UPD` structure is part of `FSPS_UPD` structure. 2. Drop `soc_fsp_multi_phase_init_is_enable()` from JSL and Xeon-SP SoCs, a SoC override to callout that SoC doesn't support calling MultiPhase Si Init is no longer required. 3. Add `FSPS_USE_MULTI_PHASE_INIT` Kconfig for SoC to specify if SoC users want to enable `EnableMultiPhaseSiliconInit` arch UPD (using `fsp_fill_common_arch_params()`) and execute FspMultiPhaseSiInit() API. 4. Presently selects `FSPS_USE_MULTI_PHASE_INIT` from IA TCSS common code. 5. Add `fsp_is_multi_phase_init_enabled()` that check applicability of MultiPhase Si Init prior calling FspMultiPhaseSiInit() API to honor SoC users' decision. 6. Drop `arch_silicon_init_params()` from SoC as FSP driver (FSP 2.2) would check the applicability of MultiPhase Si Init prior calling FspMultiPhaseSiInit() API. Additionally, selects FSPS_HAS_ARCH_UPD for Alder Lake as Alder Lake FSPS_UPD structure has `FSPS_ARCH_UPD` structure and drops `arch_silicon_init_params()` from SoC `platform_fsp_silicon_init_params_cb()`. Skip EnableMultiPhaseSiliconInit hardcoding for Tiger Lake and uses the fsp_is_multi_phase_init_enabled() function to override EnableMultiPhaseSiliconInit UPD prior calling MultiPhaseSiInit FSP API. TEST=EnableMultiPhaseSiliconInit UPD is getting set or reset based on SoC user selects FSPS_USE_MULTI_PHASE_INIT Kconfig. Change-Id: I019fa8364605f5061d56e2d80b20e1a91857c423 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-13soc/intel/tgl: Enable USB4 resources based on common KconfigFurquan Shaikh
Intel TGL BIOS specification (doc ##611569) Revision 0.7.6 Section 7.2.5.1.5 recommends reserving the following resources for each PCIe USB4 root port: - 42 buses - 194 MiB Non-prefetchable memory - 448 MiB Prefetchable memory This change enables reserving of resources for USB4 when mainboard selects the newly added Kconfig SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES. This is similar to the change for ADL in commit 8d11cdc6fa ("soc/intel/alderlake: Add Kconfig for recommended PCIe TBT resources"). Change-Id: I25ec3f74ebd5727fa4b13f5a3b11050f77ecb008 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-10soc/intel/tigerlake: Switch to runtime generation of Intel Power EngineTim Wawrzynczak
The pep.asl file is being obsoleted by runtime generation, therefore switch tigerlake boards to this method. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I8e97c589273e934e89d69d8829680b9cac1ff9f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10soc/intel/tigerlake: Move LPM functions to new fileTim Wawrzynczak
The LPM enable mask is useful to have in more than one place, therefore more the get_disable_mask() function and its helpers to lpm.c Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ibe83dc106f5f37baf9d5c64f68c47d85ea4e6dd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56460 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-08cpu/x86/tsc: Deduplicate Makefile logicAngel Pons
The code under `cpu/x86/tsc` is only compiled in when its `Makefile.inc` is included from platform (CPU/SoC) code and the `UDELAY_TSC` Kconfig option is enabled. Include `cpu/x86/tsc/Makefile.inc` once from `cpu/x86/Makefile.inc` and drop the now-redundant inclusions from platform code. Also, deduplicate the `UDELAY_TSC` guards. Change-Id: I41e96026f37f19de954fd5985b92a08cb97876c1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57456 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-02soc/intel/tigerlake: Set MAX_CPUS for TGL-H to 16Tim Crawford
TGL-H supports up to 8 cores (16 threads). Change-Id: I2ee1be37f564bf1b6249a6c223be093747c38ab5 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-26soc/intel/tigerlake: Lock PAM registers in finalizeTim Wawrzynczak
Use the support from the previous patch to have coreboot lock the PAM registers instead of the FSP when the lockdown configuration is set to coreboot. Change-Id: Ice4c727f2b75893cd012345a556fd21d9807dfaa Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-25soc/intel/tigerlake: Hook up ucode for TGL-HTim Crawford
Hook up microcode from 3rdparty repo for: - 06-8d-01 (CPUID signature: 0x806d1) Verified microcode blob was found in CBFS on system76/gaze16 (TGL-H). CBFS: Found 'cpu_microcode_blob.bin' @0x11700 size 0x18400 in mcache @0x76c2d0ac microcode: sig=0x806d1 pf=0x2 revision=0x2c Change-Id: Icf0d8bc700a73697f06503e9d1bb40ce26741cdf Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57067 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-26 13:26:53 +0000