diff options
| author | Felix Singer <felixsinger@posteo.net> | 2021-12-10 23:23:42 +0100 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2022-01-01 22:24:31 +0000 |
| commit | f424c8b80f6de3ff250126abff8b03986d1090ee (patch) | |
| tree | 8ebdf35779f498b1345c36b1784823e8f334a24d /src/soc/intel/tigerlake | |
| parent | b6519812d423f553c727d97bb004fbb5c55b60ae (diff) | |
soc/intel/tigerlake/fsp_params.c: Use `is_dev_enabled()`
Change-Id: I3e79f637bedec0bdca1312291328b2385bd027a7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Diffstat (limited to 'src/soc/intel/tigerlake')
| -rw-r--r-- | src/soc/intel/tigerlake/fsp_params.c | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 40676f1b7d..f04c3d7b5a 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -530,10 +530,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* USB4/TBT */ for (i = 0; i < ARRAY_SIZE(params->ITbtPcieRootPortEn); i++) { dev = pcidev_on_root(SA_DEV_SLOT_TBT, i); - if (dev) - params->ITbtPcieRootPortEn[i] = dev->enabled; - else - params->ITbtPcieRootPortEn[i] = 0; + params->ITbtPcieRootPortEn[i] = is_dev_enabled(dev); } /* PCH FIVR settings override */ |