summaryrefslogtreecommitdiff
path: root/src/soc/intel/tigerlake/fsp_params.c
AgeCommit message (Expand)Author
2021-03-28soc/intel/tigerlake: Move TCSS code to intel/common/blockTim Wawrzynczak
2021-03-19soc/intel/tgl: Add configurable value for PmcUsb2PhySusPgEnableDerek Huang
2021-03-15soc/intel/tigerlake: Add CNVi Bluetooth flag at devicetree entryCliff Huang
2021-03-05soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during bootBrandon Breitenstein
2021-03-05soc/tigerlake: Fix TCSS code to calling back and forth to mainboard and socBrandon Breitenstein
2021-02-22soc/intel/tigerlake: Enable end of post support in FSPNick Vaccaro
2021-02-10soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard designShreesh Chhabbi
2021-01-14soc/intel/tgl: Add configurable value for UsbTcPortEnBrandon Breitenstein
2021-01-13soc/intel/tigerlake: Disable TC cold supportSrinidhi N Kaushik
2021-01-08soc/intel/tigerlake: Enable USB2 port reset message on Type-C portsJohn Zhao
2020-11-20soc/intel/tigerlake: Expose UPD to enable Precision Time MeasurementDuncan Laurie
2020-11-13soc/intel/tigerlake: Add code for early tcssBrandon Breitenstein
2020-11-05soc/intel/tigerlake: Disable C1 C-state DemotionRavi Sarawadi
2020-10-23soc/intel/tigerlake: Add Acoustic featuresShaunak Saha
2020-09-24soc/intel/tigerlake: Add support for CnviBtCore and CnviBtAudioOffloadJohn Zhao
2020-09-23soc/intel/tigerlake: Configure FSP UPDs for minimum assertion widthsJamie Ryu
2020-09-06soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by defaultMichael Niewöhner
2020-09-02soc/intel/tigerlake: Add mainboard hook for overriding SoC configJes Klinke
2020-08-17soc/intel/tigerlake: Allow fine grained control of S0iX statesJes Klinke
2020-08-01soc/intel/{icl,jsl,tgl}: Remove SkipMpInit UPD as deprecatedSubrata Banik
2020-07-29soc/intel/tigerlake: Configure TCSS D3Hot and D3ColdJohn Zhao
2020-07-28soc/intel/tigerlake: Simplify is-device-enabled checksFelix Singer
2020-07-26src: Update bare access to BOOL CONFIG_ vals to CONFIG()Martin Roth
2020-07-21soc/intel/tigerlake: Select PLATFORM_USES_FSP2_2Subrata Banik
2020-07-15soc/intel/tigerlake: Hook up SATA Port Enable DITO UPDsShaunak Saha
2020-07-03soc/intel/tigerlake: Disable hybrid storage mode in CSE Lite RO bootJamie Ryu
2020-06-30tigerlake: enable tcc_offset functionalitySumeet R Pawnikar
2020-06-17soc/soch/intel/tigerlake: Integrate PCIe hot-plug config UPDWonkyu Kim
2020-06-12soc/intel/tigerlake: Add devicetree support to change PCH VR settingsVenkata Krishna Nimmagadda
2020-06-09soc/intel/tigerlake: Set FSPS UPD ITbtConnectTopologyTimeoutInMsJohn Zhao
2020-05-28soc/intel/tigerlake: Configure THCWonkyu Kim
2020-05-26soc/intel/tigerlake: Disable VMDWonkyu Kim
2020-05-26soc/intel/tigerlake: Add FSP UPD D3HotEnable and D3ColdEnableJohn Zhao
2020-05-20tigerlake: enable DPTF functionality for volteerSumeet R Pawnikar
2020-05-20soc/tigerlake: Add devicetree configurability for IomTypeCPortPadCfgBrandon Breitenstein
2020-05-12soc/intel/tigerlake: Control SATA and DMI power optimizationShaunak Saha
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
2020-05-01soc/intel/tigerlake: Fill PcieRpClkReqDetect from devicetreeMeera Ravindranath
2020-04-20soc/intel/tigerlake: Merge the recent change from other platformsWonkyu Kim
2020-04-14soc/intel/tigerlake: Implement CHIPSET_LOCKDOWNWonkyu Kim
2020-04-14soc/intel/tigerlake: Configure RP settingWonkyu Kim
2020-04-06soc/intel/tigerlake: Use SPDX for GPL-2.0-only filesAngel Pons
2020-04-01soc/intel/tigerlake: Remove Jasper Lake SoC referencesAamir Bohra
2020-01-13soc/intel/tigerlake: Select correct fsp_param as per SoC KconfigMaulik V Vaghela
2019-12-11soc/intel/tigerlake: Include soc common lpss header fileAamir Bohra
2019-11-09soc/intel/tigerlake: Do initial SoC commit till ramstageSubrata Banik