| Age | Commit message (Expand) | Author |
|---|---|---|
| 2020-02-01 | soc/intel/tigerlake: Configure TCSS xHCI and xDCI | Wonkyu Kim |
| 2020-01-28 | soc/intel/tigerlake: Enable DP ports according to board design | Wonkyu Kim |
| 2020-01-18 | soc/intel/tigerlake: Update chip files | Ravi Sarawadi |
| 2019-12-12 | soc/intel/{cnl,icl,skl,tgl}: Remove unused gpe0_en_* from chip.h | Furquan Shaikh |
| 2019-11-09 | soc/intel/tigerlake: Do initial SoC commit till ramstage | Subrata Banik |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |