| Age | Commit message (Expand) | Author |
|---|---|---|
| 2024-03-05 | soc/intel/tigerlake: Add IRQ mapping for PEG PCI-E ports | Alicja Michalska |
| 2023-10-23 | soc/intel/tigerlake: Add ACPI devices for FSPI, SRAM, HEC1 | Matt DeVillier |
| 2021-08-24 | soc/intel/tigerlake: Add TGL-H PEG ports | Jeremy Soller |
| 2021-08-24 | soc/intel/tigerlake: Add PCIe root ports for PCH-H | Jeremy Soller |
| 2020-05-11 | treewide: Remove "this file is part of" lines | Patrick Georgi |
| 2020-04-06 | soc/intel/tigerlake: Use SPDX for GPL-2.0-only files | Angel Pons |
| 2020-03-18 | soc: Remove copyright notices | Patrick Georgi |
| 2020-03-15 | soc/intel/tigerlake: Match RP number with TGL EDS | Wonkyu Kim |
| 2019-11-09 | soc/intel/tigerlake/acpi: Copy acpi directory from icelake | Subrata Banik |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |