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authorJeremy Soller <jeremy@system76.com>2021-08-12 10:49:58 -0600
committerFelix Held <felix-coreboot@felixheld.de>2021-08-24 14:49:33 +0000
commitbc071feec18fb7feffbcacde74d101348c65e98e (patch)
tree3000fdc6a32fe37f7dc6b01bc9132cf8b3cdcdc9 /src/soc/intel/tigerlake/acpi/pcie.asl
parent83d795c45b602ed1736e80871b2bd5cd2ccf7490 (diff)
soc/intel/tigerlake: Add TGL-H PEG ports
Change-Id: I2d61532c9803972473a8cd45127d55b8cdeab06e Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/tigerlake/acpi/pcie.asl')
-rw-r--r--src/soc/intel/tigerlake/acpi/pcie.asl22
1 files changed, 22 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/acpi/pcie.asl b/src/soc/intel/tigerlake/acpi/pcie.asl
index 8219c653a7..9c98dde129 100644
--- a/src/soc/intel/tigerlake/acpi/pcie.asl
+++ b/src/soc/intel/tigerlake/acpi/pcie.asl
@@ -112,6 +112,28 @@ Method (IRQM, 1, Serialized) {
}
}
+Device (PEG0)
+{
+ Name (_ADR, 0x00060000)
+}
+
+#if CONFIG(SOC_INTEL_TIGERLAKE_PCH_H)
+Device (PEG1)
+{
+ Name (_ADR, 0x00010000)
+}
+
+Device (PEG2)
+{
+ Name (_ADR, 0x00010001)
+}
+
+Device (PEG3)
+{
+ Name (_ADR, 0x00010002)
+}
+#endif
+
Device (RP01)
{
Name (_ADR, 0x001C0000)