coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2019-03-08	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	Julius Werner
2019-01-09	soc/intel: Clean mess around UART_DEBUG	Nico Huber
2018-08-20	soc/intel/common/block: Move common uart function to block/uart	Subrata Banik
2018-05-22	bootblock: Allow more timestamps in bootblock_main_with_timestamp()	Julius Werner
2017-12-22	ic2/designware: Move Intel i2c logic to shared driver	Chris Ching
2017-07-01	soc/intel/skylake: Remove unnecessary P-State and Flex Ratio assignment	Barnali Sarkar
2017-05-18	intel/common/block/i2c: Add common block for I2C and use the same in SoCs	Rizwan Qureshi
2017-04-06	soc/intel/skylake: Add support for GSPI controller	Furquan Shaikh
2017-03-17	soc/intel/skylake: Fix remaining issues detected by checkpatch	Lee Leahy
2016-11-30	soc/skylake: Move IO decode range out from pch_lpc_init	Teo Boon Tiong
2016-11-28	soc/intel/skylake: Initialize UART based on CONFIG_UART_DEBUG	Teo Boon Tiong
2016-08-18	soc/intel/skylake: Move bootblock specific code from skylake/romstage	Naresh G Solanki
2016-08-18	skylake: Do FspTempRamInit only for FSP1.1 & tidy up PCH early init	Rizwan Qureshi
2016-07-28	intel/fsp1_1: Add C entry support to locate FSP Temp RAM Init	Subrata Banik
2016-07-28	soc/intel/skylake: Add C entry bootblock support	Subrata Banik
2016-07-28	soc/intel/skylake: Do cache as ram and prepare for C entry	Subrata Banik