soc/intel/skylake: Add C entry bootblock support

List of activity performing in this patch
- early PCH programming
- early SA programming
- early CPU programming
- mainborad early gpio programming for UART and SPI
- car setup
- move chipset programming from verstage to post console

BUG=chrome-os-partner:55357
BRANCH=none
TEST=Built and booted kunimitsu till POST code 0x34

Change-Id: If20ab869de62cd4439f3f014f9362ccbec38e143
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/15785
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 26 insertions, 1 deletions

diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c
index c7ec937566..028bb7b314 100644
--- a/src/soc/intel/skylake/bootblock/bootblock.c
+++ b/src/soc/intel/skylake/bootblock/bootblock.c
@@ -14,9 +14,34 @@
  */
 
 #include <bootblock_common.h>
+#include <soc/bootblock.h>
+#include <soc/romstage.h>
 
 void asmlinkage bootblock_c_entry(uint64_t base_timestamp)
 {
 	/* Call lib/bootblock.c main */
 	bootblock_main_with_timestamp(base_timestamp);
-}
\ No newline at end of file
+}
+
+void bootblock_soc_early_init(void)
+{
+	bootblock_systemagent_early_init();
+	bootblock_pch_early_init();
+	bootblock_cpu_init();
+
+	if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE))
+		pch_uart_init();
+}
+
+/*
+ * Perform early chipset initialization before fsp memory init
+ * example: pirq->irq programming, enabling smbus, pmcbase, abase,
+ * 			get platform info, i2c programming
+ */
+void bootblock_soc_init(void)
+{
+	report_platform_info();
+	set_max_freq();
+	pch_early_init();
+	i2c_early_init();
+}