| Age | Commit message (Expand) | Author |
|---|---|---|
| 2016-11-30 | soc/skylake: Move IO decode range out from pch_lpc_init | Teo Boon Tiong |
| 2016-11-28 | soc/intel/skylake: Initialize UART based on CONFIG_UART_DEBUG | Teo Boon Tiong |
| 2016-08-18 | soc/intel/skylake: Move bootblock specific code from skylake/romstage | Naresh G Solanki |
| 2016-08-18 | skylake: Do FspTempRamInit only for FSP1.1 & tidy up PCH early init | Rizwan Qureshi |
| 2016-07-28 | intel/fsp1_1: Add C entry support to locate FSP Temp RAM Init | Subrata Banik |
| 2016-07-28 | soc/intel/skylake: Add C entry bootblock support | Subrata Banik |
| 2016-07-28 | soc/intel/skylake: Do cache as ram and prepare for C entry | Subrata Banik |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |