| Age | Commit message (Expand) | Author |
|---|---|---|
| 2024-08-30 | soc/intel/meteorlake: Configure DDR5 Physical channel width to 64 | Arthur Heymans |
| 2024-05-30 | soc/intel/meteorlake: Adjust FSP parameters for FSP2.4 compatibility | Appukuttan V K |
| 2022-08-25 | soc/intel/mtl: Hook up Lp5CccConfig FSP UPD | Kapil Porwal |
| 2022-08-25 | soc/intel/mtl: Hook up ECT FSP UPD | Kapil Porwal |
| 2022-06-29 | soc/intel/mtl: Do initial Meteor Lake SoC commit till romstage | Ravi Sarawadi |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |