coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2023-06-29	soc/intel/meteorlake: Add QS(C0) stepping CPU ID	Musse Abdullahi
2023-04-15	soc/intel/meteorlake: Add B0 stepping CPU ID	Musse Abdullahi
2023-02-10	soc/intel/{common, meteorlake}: Add support for new MCH	Sridhar Siricilla
2022-11-26	src/soc/intel: Remove unnecessary space after casts	Elyes Haouas
2022-11-18	soc/intel/meteorlake: Add Meteor Lake MCH device ID	Sridhar Siricilla
2022-11-17	soc/intel/meteorlake: Implement report_cache_info() function	Dinesh Gehlot
2022-11-15	soc/intel: Add Meteor Lake IGD device id 0x7d45	Ravi Sarawadi
2022-11-04	soc/intel: Include <cpu/cpu.h> instead of <arch/cpu.h>	Elyes Haouas
2022-08-25	soc/intel/mtl: Program MCHBASE prior enabling extended bios range	Subrata Banik
2022-07-07	soc/intel/common/graphics: Add another Meteor Lake device ID	Wonkyu Kim
2022-06-22	soc/intel: Add Meteor Lake SA device ID	Subrata Banik
2022-06-06	soc/intel/meteorlake: Refactor bootblock SoC programming code	Subrata Banik
2022-06-06	soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock	Ravi Sarawadi