| Age | Commit message (Expand) | Author |
|---|---|---|
| 2016-03-13 | intel/fsp_baytrail: Fix LPE initialization and enable ACPI mode | Ben Gardner |
| 2016-02-10 | soc/fsp_baytrail: Add support for FSP MR 005 | Ben Gardner |
| 2016-01-29 | src/: Chmod 644 all .c, .h, .asl, .inc, .cb, .hex, & Kconfig files | Martin Roth |
| 2015-10-31 | tree: drop last paragraph of GPL copyright header | Patrick Georgi |
| 2015-07-21 | intel/fsp_baytrail: Support Baytrail FSP Gold4 release | York Yang |
| 2015-05-21 | Remove address from GPLv2 headers | Patrick Georgi |
| 2015-04-24 | fsp: Move fsp to fsp1_0 | Marc Jones |
| 2014-12-05 | fsp_baytrail: remove register option for TSEG size | Martin Roth |
| 2014-12-05 | fsp_baytrail: update to add the UPD_DEFAULT_CHECK macro | Martin Roth |
| 2014-12-01 | Mark non-executable files non-executable | Patrick Georgi |
| 2014-11-21 | intel/fsp_baytrail: add Gold3 FSP support | York Yang |
| 2014-11-19 | fsp_baytrail: Update chip.h UPD entries to match names in fspvpd.h | Martin Roth |
| 2014-05-29 | fsp_baytrail: Add the FSP version of Intel's Bay Trail-I chip | Martin Roth |
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index : coreboot.git | |
| my copy of coreboot | gitea |
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