diff options
| author | Martin Roth <martin.roth@se-eng.com> | 2014-11-16 20:28:57 -0700 |
|---|---|---|
| committer | Martin Roth <gaumless@gmail.com> | 2014-12-05 16:23:08 +0100 |
| commit | 30eda3edd72f70b3ff7ef46f5cb6e0e346683062 (patch) | |
| tree | fe77ef3ed78f6dec5ebc512ccc268a7c61fd30f3 /src/soc/intel/fsp_baytrail/chip.h | |
| parent | bdfe98f92fc1e9a69aa30ba87bb679dc28e9727c (diff) | |
fsp_baytrail: remove register option for TSEG size
Set the UPD entry based on the Kconfig value instead of having two
separate places that the value needs to be set.
Change-Id: I3d32111b59152d0a8fc49e15320c7b5a140228a6
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7490
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
Diffstat (limited to 'src/soc/intel/fsp_baytrail/chip.h')
| -rw-r--r-- | src/soc/intel/fsp_baytrail/chip.h | 14 |
1 files changed, 0 insertions, 14 deletions
diff --git a/src/soc/intel/fsp_baytrail/chip.h b/src/soc/intel/fsp_baytrail/chip.h index df1d57e471..6e83ef236f 100644 --- a/src/soc/intel/fsp_baytrail/chip.h +++ b/src/soc/intel/fsp_baytrail/chip.h @@ -52,20 +52,6 @@ struct soc_intel_fsp_baytrail_config { #define SATA_MODE_AHCI INCREMENT_FOR_DEFAULT(1) /* - * MrcInitTsegSize - * 0x01, "1 MB" - * 0x02, "2 MB" - * 0x04, "4 MB" - * 0x08, "8 MB" - */ - uint16_t PcdMrcInitTsegSize; - #define TSEG_SIZE_DEFAULT UPD_DEFAULT - #define TSEG_SIZE_1_MB INCREMENT_FOR_DEFAULT(1) - #define TSEG_SIZE_2_MB INCREMENT_FOR_DEFAULT(2) - #define TSEG_SIZE_4_MB INCREMENT_FOR_DEFAULT(4) - #define TSEG_SIZE_8_MB INCREMENT_FOR_DEFAULT(8) - - /* * MrcInitMmioSize * 0x400, "1.0 GB"s * 0x600, "1.5 GB" |