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2021-05-05soc/intel/common/block: Add definition for NAF_VWE bit for PAD_CFG0 regMaulik V Vaghela
Earlier we did not have definition for BIT27 for PAD_CFG0 register, we will use this BIT to enable "virtual wire messaging for native function" If this bit is enabled, whenever change is detected on the pad, virtual wire message is generated and sent to destination set by native function. This bit must be set while enabling CPU PCIe root port programming for ADL and thus defining a new macro to set native pad function along with NAF_VWE bit to make GPIO programming easier from coreboot. BUG=None BRANCH=None TEST=Code compilation works fine and if we use this macro to program GPIO, proper bit is getting set in PAD_CFG register Change-Id: I732e68b413eb01b8ae1a4927836762c8875b73d2 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52782 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-05drivers/intel/fsp2_0: Fix the FSP-T positionArthur Heymans
The only use case for FSP-T in coreboot is for 'Intel Bootguard' support at the moment. Bootguard can do verification FSP-T but there is no verification on whether the FSP found by walkcbfs_asm is the one actually verified as an IBB by Bootguard. A fixed pointer needs to be used. TESTED on OCP/Deltalake, still boots. Change-Id: I1ec8b238384684dccf39e5da902d426d3a32b9db Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-04-28soc/intel/common/block/hda: Use azalia device codePatrick Rudolph
The code is already compiled in on all platforms. Use it as it provides the same functionality. Note that GCAP is no longer R/WO on these platforms. However, select `AZALIA_LOCK_DOWN_R_WO_GCAP` just in case. This will be dropped in a follow-up. Tested on Prodrive Hermes, still detects and initializes both codecs. Change-Id: I75424559b2b4aca63fb23bf4f8d5074aa1e1bb31 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50795 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28soc/intel: Add Z370, H310C and B365 device IDsAngel Pons
Intel document 335192-004 contains the PCI device IDs for Z370 and H310C, but lacks the ID for B365. The ID appears on some websites: https://linux-hardware.org/index.php?id=pci:8086-a2cc-1849-a2cc Change-Id: Iea3c435713c46854c5271fbc266f47ba4573db52 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52703 Reviewed-by: Timofey Komarov <happycorsair@yandex.ru> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28soc/intel: Add Kaby Lake PCH-U base device IDAngel Pons
Taken from Intel document 334658-003 (7th Generation Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel Processor Family I/O for U Quad Core Platforms, Datasheet - Volume 1 of 2). Change-Id: I1d48c8868e1e5d453d599ecec835938ce09935d0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52702 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Timofey Komarov <happycorsair@yandex.ru> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28soc/intel: Rename 200-series PCH device IDsAngel Pons
The code name for these PCHs is Union Point, abbreviated as `UPT`. There are some 300-series Union Point PCHs (H310C, B365, Z370) which are meant to be paired with Coffee Lake CPUs instead of Skylake or Kaby Lake CPUs, and referring to them as `KBP` (Kaby Point, I guess) would be confusing. Tested with BUILD_TIMELESS=1, HP 280 G2 remains identical. Change-Id: I1a49115ae7ac37e76ce8d440910fb59926f34fac Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52700 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Timofey Komarov <happycorsair@yandex.ru> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-22soc/intel/common,skl: set MSR LT_LOCK_MEMORY once, not per threadMichael Niewöhner
The MSR LT_LOCK_MEMORY is package-scoped, not thread-scoped. Only set it once. Tested on Acer ES1-572 by checking chipsec results. Change-Id: If3d61fcbc9ab99b6c1b7b74881e6d9c6be04a498 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-21soc/intel/alderlake: rename CONFIG_MAX_PCIE_CLOCKS to CONFIG_MAX_PCIE_CLOCK_SRCRizwan Qureshi
CONFIG_MAX_PCIE_CLOCKS renamed to MAX_PCIE_CLOCK_SRC to make it clear that this config is for the number of PCIe Clock sources available which is different from PCIe clock reqs. This is more relevant in alderlake, as the number clock source and clock reqs differ. However since this is a better name, renaming it throughout the soc/intel tree. Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Change-Id: I747c94331b68c4ec0b6b5a04149856a4bb384829 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52194 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21soc/intel/common/smbus: lock TCO base address on PCH finalizeMichael Niewöhner
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Idab9419487e6e4cbdecd2efaa4772ff4960c9055 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2021-04-21{sb,soc}/intel: Use `get_int_option` functionAngel Pons
Change-Id: I05f724785880089a513319d70dfd70fc2a6b7679 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-04-19soc/intel/common/block/smm: Drop stale commentAngel Pons
This comment is most likely a copy-paste leftover from Braswell. Change-Id: I49bfa3cc56539df0b47d2e2bd74b2bfc45421034 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-19soc/intel/common/block/pcr: Define __SIMPLE_DEVICE__Angel Pons
Change-Id: I06f9c623947e48a7213e42507f4da51c12b425d7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-19soc/intel/common/block/smbus: Define __SIMPLE_DEVICE__Angel Pons
Change-Id: I93f7918763d87f8fb50f39f9469694e73aeff37b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-16soc/intel/common/gpio: Implement GPIO snapshot/verify callbacksFurquan Shaikh
This change implements `gpio_snapshot()` and `gpio_verify_snapshot()` callbacks that are useful for debugging any GPIO configuration changes across FSP-S. These can be utilized by all Intel SoCs that make use of the common block GPIO driver. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I82a1f125c490b9d6e26e6e9527c2fcd55bb9d429 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-16soc/intel/common/block/fast_spi: Add flash PRR34 lockMarc Jones
Set the flash PRR3 and PRR4 lock to be set with SPI FLOCKDN. Change-Id: I288eea3e0e853e5067c5af23e22eab79330c0f20 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51779 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-15src/*acpi: create acpi table for x2apic modeWonkyu Kim
Create acpi table for x2apic nmi, apic_ids BUG=None BRANCH=None TEST=boot to OS and check apic mode cat /proc/cpuinfo | grep "apicid" Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I9399d30b686b55d86806f5db4110bf4a80fe459b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-04-14intel: mma: Use new CBFS APIJulius Werner
This patch changes the Intel MMA driver to use the new CBFS API. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Icc11d0c2a9ec1bd7a1d6af362f849dac16375433 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-04-06soc/intel/common: Prevent SMI storm when setting SPI WPD bitAngel Pons
From Skylake/Sunrise Point onwards, there are two BIOS_CNTL registers: one on the LPC/eSPI PCI device, and another on the SPI PCI device. When the WPD bit changes from 0 to 1 and the LE bit is set, the PCH raises a TCO SMI with the BIOSWR_STS bit set. However, the BIOSWR_STS bit is not set when the TCO SMI comes from the SPI or eSPI controller instead, but a status bit in the BIOS_CNTL register gets set. If the SMI cause is not handled, another SMI will happen immediately after returning from the SMI handler, which results in a deadlock. Prevent deadlocks by clearing the SPI synchronous SMI status bit in the SMI handler. When SPI raises a synchronous SMI, the TCO_STS bit in the SMI_STS register is continously set until the SPI synchronous SMI status bit is cleared. To not risk missing any other TCO SMIs, do not clear the TCO_STS bit again in the same SMI handler invocation. If the TCO_STS bit remains set when returning from SMM, another SMI immediately happens and clears the TCO_STS bit, handling any pending events. SPI can also generate asynchronous SMIs when the WPD bit is cleared and one attempts to write to flash using SPI hardware sequencing. This patch does not account for SPI asynchronous SMIs, because they are disabled by default and cannot be enabled once the BIOS Interface Lock-Down bit in the BIOS_CNTL register has been set, which coreboot already does. These asynchronous SMIs set the SPI_STS bit of the SMI_STS register. Clearing the SPI asynchronous SMI source should be done inside the SPI_STS SMI handler, which is currently not implemented. All of this goes out of the scope of this patch, and is currently not necessary anyway. This patch does not handle eSPI because I cannot test it, and knowing if a board uses LPC or eSPI from common code is currently not possible, and this is beyond the scope of what this commit tries to achieve (fix SPI). Tested on HP 280 G2, no longer deadlocks when SMM BIOS write protection is on. Write protection will be enforced in a follow-up. Change-Id: Iec498674ae70f6590c33a6bf4967876268f2b0c8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50754 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06soc/intel/alderlake: Add LPC and IGD device Ids for Alderlake MMaulik V Vaghela
Added new LPC and IGD device IDs for Alderlake M. Also, added entry for CPUID_ALDERLAKE_M_A0 in report_platform.c TEST=Check if platform information print is coming properly in coreboot Change-Id: If33c43da8cbd786261b00742e342f0f01622c607 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50138 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05device/dram/ddr3: Rename DDR3 SPD memory typesAngel Pons
To avoid name clashes with definitions for other DRAM generations, rename the enum type and values to contain `ddr3` or `DDR3`. Change-Id: If3710149ba94b94ed14f03e32f5e1533b4bc25c8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51896 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28soc/intel/common/gpio: Add function to get GPIO index in groupTim Wawrzynczak
The gpio_get_index_in_group function returns the index of the GPIO within its own group Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I7f6b312bd1d0388ef799cd127c88b17bad6a3886 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-28soc/intel/common/systemagent: Add macros to access REGBAR spaceTim Wawrzynczak
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I97203aca377d4dd77e03b2c83fdd20a2874cc1c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51755 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28soc/intel/common/tcss: Rename TCSS_DISPLAYTim Wawrzynczak
This name isn't very meaningful, rename the config option to ENABLE_TCSS_DISPLAY_DETECTION to make its meaning more obvious. Change-Id: Ib21a3b5a37d25f93bd515f8c6e5ad39c9d2ea1c4 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51771 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28soc/intel/tigerlake: Move TCSS code to intel/common/blockTim Wawrzynczak
The Type-C subsystem ("TCSS") IP block is similar between TGL and ADL. For pre-boot purposes, the limited amount of functionality required appears to be common between the two, therefore move the functionality to intel/common/block and rename from `early_tcss to `tcss` along the way. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I1c6bb9c7098691f0c828f9d5ab4bd522515ae966 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51753 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-27soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.hSubrata Banik
Lists of changes: 1. Rename MISCCFG_ENABLE_GPIO_PM_CONFIG -> MISCCFG_GPIO_PM_CONFIG_BITS 2. Move MISCCFG_GPIO_PM_CONFIG_BITS definition from intelblock/gpio.h to soc/gpio.h. Refer to detailed description below to understand the motivation behind this change. An advanced GPIO PM capabilities has been introduced since CNP PCH, refer to 'include/intelblock/gpio.h' for detailed GPIO PM bit definitions. Now with TGP PCH, additional bits are defined in the MISCCFG register for GPIO PM control. This results in different SoCs supporting different number of bits. The bits defined in earlier platforms (CNL, CML, ICL) are present on TGL, JSL and ADL too. Hence, refactor the common GPIO code to keep the bit definitions in intelblock/gpio.h, but the definition of MISCCFG_GPIO_PM_CONFIG_BITS is moved to soc/gpio.h so that each SoC can provide this as per hardware support. TEST=On ADL, TGL and JSL platform. Without this CL : GPIO COMM 0 MISCCFG:0xC0 (Bit 6 and 7 enable) With this CL : GPIO COMM 0 MISCCFG: 0x00 (Bit 6 and 7 disable) Change-Id: Ie027cbd7b99b39752941384339a34f8995c10c94 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-27soc/intel/common/block/gpio: Fix typecasting issueSubrata Banik
This patch fixes unsigned conversion from 'int' to 'uint8_t' {aka 'const unsigned char'} changes value from '-256' to '0' [-Werror=overflow]. Change-Id: Ifcc42e5a2ff06f0af0eb96bef4c6044cbcdbd94b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-22soc/intel/common/hda_verb.c: Fix up comment styleAngel Pons
Change-Id: I31c541fb197aca33ef64d2972a32924b61fd015c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-03-22acpi/acpigen.h: Add more intuitive AML package closing functionsJakub Czapiga
Until now every AML package had to be closed using acpigen_pop_len(). This commit introduces set of package closing functions corresponding with their opening function names. For example acpigen_write_if() opens if-statement package, acpigen_write_if_end() closes it. Now acpigen_write_else() closes previously opened acpigen_write_if(), so acpigen_pop_len() is not required before it. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Icfdc3804cd93bde049cd11dec98758b3a639eafd Reviewed-on: https://review.coreboot.org/c/coreboot/+/50910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-18soc/intel/block/cpu/mp_init.c: Remove weak functionsArthur Heymans
All platforms implement those and using a no-op function is not expected, so it is better to fail the build if the soc specific code is not implemented. Change-Id: Id946f5b279dcfa6946381b9a67faba6b8c1ca332 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51522 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-17spd_bin: Replace get_spd_cbfs_rdev() with spd_cbfs_map()Julius Werner
In pursuit of the goal of eliminating the proliferation of raw region devices to represent CBFS files outside of the CBFS core code, this patch removes the get_spd_cbfs_rdev() API and instead replaces it with spd_cbfs_map() which will find and map the SPD file in one go and return a pointer to the relevant section. (This makes it impossible to unmap the mapping again, which all but one of the users didn't bother to do anyway since the API is only used on platforms with memory-mapped flash. Presumably this will stay that way in the future so this is not something worth worrying about.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Iec7571bec809f2f0712e7a97b4c853b8b40702d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-15pciexp_device: Rewrite LTR configurationNico Huber
I was bugged by spurious "Failed to enable LTR" messages for years. Looking at the the current algorithm, it is flawed in multiple ways: * It looks like the author didn't know they implemented a recursive algorithm (pciexp_enable_ltr()) inside another recursive algorithm (pciexp_scan_bridge()). Thus, at every tree level, everything is run again for the whole sub- tree. * LTR is enabled no matter if `.set_ltr_max_latencies` is implemented or not. Leaving the endpoints' LTR settings at 0: They are told to always report zero tolerance. In theory, depending on the root-complex implementation, this may result in higher power consumption than without LTR messages. * `.set_ltr_max_latencies` is only considered for the direct parent of a device. Thus, even with it implemented, an endpoint below a (non-root) bridge may suffer from the 0 settings as described above. * Due to the double-recursive nature, LTR is enabled starting with the endpoints, then moving up the tree, while the PCIe spec tells us to do it in the exact opposite order. With the current implementation of pciexp_scan_bridge(), it is hard to hook anything in that runs for each device from top to bottom. So the proposed solution still adds some redundancy: First, for every device that uses pciexp_scan_bus(), we enable LTR if possible (see below). Then, when returning from the bus- scanning recursion, we enable LTR for every device and configure the maximum latencies (if supported). The latter runs again on all bridges, because it's hard to know if pciexp_scan_bus() was used for them. When to enable LTR: * For all devices that implement `.set_ltr_max_latencies`. * For all devices below a bridge that has it enabled already. Change-Id: I2c5b8658f1fc8cec15e8b0824464c6fc9bee7e0e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51328 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-13soc/intel/common/fast_spi: Fix check-fmap-16mib-crossing checkFurquan Shaikh
Currently, `check-fmap-16mib-crossing` compares the offset and end of each SPI flash region to 16MiB to ensure that no region is placed across this 16MiB boundary from the start of SPI flash. What really needs to be checked is that the region isn't placed across the 16MiB boundary from the end of BIOS region. Thus, current check works only if the SPI flash is 32MiB under the assumption that the BIOS region is mapped at the top of SPI flash. However, this check will not work if a flash part greater than 32MiB is used. This change replaces the hardcoded boundary value of 16MiB with a value calculated by subtracting 16MiB from the SPI flash size (if it is greater than 16MiB). This calculated value is used as the boundary that no region defined in the flashmap should be placed across. The assumption here is that BIOS region is always placed at the top of SPI flash. Hence, the standard decode window would be from end_of_flash - 16M to end_of_flash (because end_of_flash = end_of_bios_region). Currently, there is no consistency in the name used for BIOS region in flashmap layout for boards in coreboot. But all Intel-based boards (except APL and GLK) place BIOS region at the end of SPI flash. Since APL and GLK do not support the extended window, this check does not matter for these platforms. Change-Id: Icff83e5bffacfd443c1c3fbc101675c4a6f75e24 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51359 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-13soc/intel/fast_spi/Makefile: Rewrite 16mib check for legibilityNico Huber
Perform some cosmetical changes: * Override the first prerequisite so we can use `$<`. * Add/remove whitspace to align things (recipe needs to be indented by a single tab only). * We can use shell variables inside double quotes. To make the end of the variable name clear, use braces, e.g. "${x}". NB. Most of the double quotes are unnecessary. They only change the way the script would be failing in case of spurious whitespace. * Break some lines doing multiple things at once. * To reduce remaining clutter, put reading numbers into a shell function. And functional changes: * No need to spawn `cat`, the shell can redirect input as well as output (using `<`). * To read a number from the `fmap_config.h`, we spawned 4 processes where a single one can achieve the same. With one exception: GNU awk refuses to parse hex numbers by default. Luckily, it turned out that we don't need intermediate decimal numbers: Shells can do arithmetic with hex values as well. Change-Id: Ia7bfba0d7864fc091ee6003e09b705fd7254e99b Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-13soc/intel/fast_spi/Makefile: Fix exit of 16mib-check recipeNico Huber
Currently, if everything worked fine, `$fail` will be unset, leading to the following `if` statement: if [ -eq 1 ] Resulting in the error message: /bin/sh: line 9: [: -eq: unary operator expected Fix this by removing the whole `if`, we can just use `exit`. Change-Id: I1bc7508d2a45a2bec07ef46b9c5d9d0b740fbc74 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-12device: Give `pci_ops.set_L1_ss_latency` a proper nameNico Huber
Rename `set_L1_ss_latency` to what it does: `set_ltr_max_latencies`. TEST=Built google/brya0 with BUILD_TIMELESS=1: no changes. Change-Id: I7008aa18bf80d6709dce1b2d3bfbb5ea407a0574 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51326 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-12soc/intel/common/block/fast_spi: Clean up headerAngel Pons
Suffix `SPIBAR_HWSEQ_XFER_TIMEOUT` with its units, use lowercase for hex values and rename BIOS_CONTROL macros, as the register is not in SPIBAR. Change-Id: I3bc1f5a5ebc4c562536829e63550c0b562b67874 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-12soc/intel/*: drop UART pad configuration from common codeMichael Niewöhner
UART pad configuration should not be done in common code, because that may cause short circuits, when the user sets a wrong UART index. Since all boards do pad setup on their own now, finally drop the pad configuration from SoC common code. Change-Id: Id03719eb8bd0414083148471ed05dea62a895126 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao
2021-03-11soc/intel/common/block/cpu: Use tab instead of spaceSubrata Banik
Convert the lines starts with whitespace with tab as applicable. TEST=Built google/brya0 and ADLRVP with BUILD_TIMELESS=1: no changes. Change-Id: Ibd11ad12caa1be866a851a8cd4bd23349e8ffbbe Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51375 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-11soc/intel/common/block: Add PCI IDs for EmmitsBurg PCHJonathan Zhang
According to Intel EmmitsBurg EDS, doc# 606161: * Add PCI devid for SPI. * Add PCI devid for ESPI (LPC). EmmitsBurg (EBG) PCH is used in the chipset with Sapphire Rapids Scalable Processor (SPR-SP). Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ie8925cb739c95c34febf9002149de437d19c8234 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-10soc/intel/common/block/smm: Ignore PM1 and GPE0 events in SCI modeAngel Pons
When the SCI_EN bit is set, PM1 and GPE0 events will trigger a SCI instead of a SMI#. However, SMI_STS bits PM1_STS and GPE0_STS can still be set. Therefore, when SCI_EN is set, ignore PM1 and GPE0 events in the SMI# handler, as these events have triggered a SCI. Do not ignore any other SMI# types, since they cannot cause a SCI. Note that these bits are reserved on APL and GLK. However, SoC-specific code already accounts for it. Thus, no special handling is needed here. Change-Id: I5998b6bd61d796101786b57f9094cdaf0c3dfbaa Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-09soc/intel/common/pch: Add server PCH optionMarc Jones
Add a server Kconfig option to select a subset of common PCH devices. Client devices are included if server isn't selected. This maintains the current Kconfig behavior. Change-Id: If11d1a51192dd87ad770b8aa53ce02b6a28b8da8 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2021-03-05soc/intel/common/block/cpu: Use tab instead of spaceSubrata Banik
Convert the lines starts with whitespace with tab as applicable. Change-Id: Ife7b27360661cbfd2c90e2b643ed31225ded228c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51250 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03soc/intel/common/block/smbus: Add config to use ACPIMaxim Polyakov
Change-Id: Iafa7d40fc21e62f99dbdc2001ab6525a2a77ff50 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44865 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03soc/intel: Factor out common smmrelocate.cAngel Pons
There are seven identical copies of the same file. One is enough. Change-Id: I68c023029ec45ecfaab0e756fce774674bb02871 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50937 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel: Factor out common smbus.hAngel Pons
Change-Id: I31bb406bd2cf371ee935aa31777307043b2ee61a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50942 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel: Factor out common gpe.hAngel Pons
The definitions are identical across seven platforms. Unify them. Change-Id: I32bbd0777f8ca9d0362d210b43e0ba8dd0c8d79b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50940 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel: Factor out identical acpigen GPIO helpersAngel Pons
Change-Id: I27f198d403f6ba05ba72ae0652da224d4cbf323a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50938 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel: Include gfx.asl from northbridgeAngel Pons
The iGPU is on the northbridge or system agent, not the southbridge. Change-Id: Ic63a7ad532fd1faa8e90d44bf7269040fa901757 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-01soc/intel/common/gpio: Add gpio_routes_ioapic_irq functionTim Wawrzynczak
This function returns true if any GPIO pad is programmed to route the given IRQ to the IO-APIC. It does so by keeping track of which pads are routed to IOxAPIC and looking this up in the new function. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Iceda89cb111caa15056c204b143b4a17d59e523e Reviewed-on: https://review.coreboot.org/c/coreboot/+/49407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-01memory_info.h: Store SMBIOS error correction typeAngel Pons
There are platforms that support error correction types other than single-bit ECC. Extend meminfo to accomodate additional ECC types. It is assumed that `struct memory_info` is packed to save space. Thus, use `uint8_t` instead of an enum type (which are usually 4 bytes wide). Change-Id: I863f8e34c84841d931dfb8d7067af0f12a437e36 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50178 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-23intel/common/block/cpu: Add APIs to get CPU info from lapic IDAamir Bohra
Add support to get core, package and thread ID from lapic ID. Implementation uses CPUID extended topology instruction to derive bit offsets for core, package and thread info in apic ID. BUG=b:179113790 Change-Id: If26d34d4250f5a88bdafacdd5d56b8882b69409e Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-02-22soc/intel/tigerlake: Add CrashLog implementation for intel TGLFrancois Toguo
CrashLog is a diagnostic feature for Intel TGL based platforms. It is meant to capture the state of the platform before a crash. The state of relevant registers is preserved across a warm reset. BUG=None TEST=CrashLog data generated, extracted, processed, decoded sucessfully on delbin. Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com> Change-Id: Ie3763cebcd1178709cc8597710bf062a30901809 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-18soc/intel/common: Drop unused `fast_spi_flash_read_wpsr` functionAngel Pons
Also remove one macro that was only used inside that function. Change-Id: Id798e08375c5757aa99288ca4a7df923309f4d67 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-18soc/intel/common/block/fast_spi: Define __SIMPLE_DEVICE__Angel Pons
Change-Id: Iff6111ab379229daec7a3892c330de6b5f0e5157 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-17soc/intel/common/block/memory: Always write `data->spd_len`Angel Pons
The `data->spd_len` option always needs to be initialised. However, it did not get set when using a mixed memory topology. Correct this bug. Fixes: commit 859ca18ced83ed3b8b529112da5f214ede3d38b0 Change-Id: I8a165f000e5d52e49de18d7648d02fe76d2dd296 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50786 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-17soc/intel/common/block/smbus: Remove unused macroSubrata Banik
TEST=Able to build and boot ADLRVP. Change-Id: Ic92271700185977f0be83cbc1d3adde37d5b6253 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-16soc/intel/common: Remove unused <string.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strstr\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/)|grep '<' Change-Id: I4cdf64119e9bfa377520d7e343434f5a6ddab3a8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-16ACPI: Add acpi_reset_gnvs_for_wake()Kyösti Mälkki
With chipset_power_state filled in romstage CBMEM hooks and GNVS allocated early in ramstage, GNVS wake source is now also filled for normal boot path. Change-Id: I2d44770392d14d2d6e22cc98df9d1751c8717ff3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-14ACPI: Move common _PIC methodKyösti Mälkki
Change-Id: I659835354570fb1d4860fcbddf2a51831170a374 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-11ACPI: Move PICM declarationKyösti Mälkki
Variable PICM was not inside GNVS region and can use a static initialisation value. For most AMD platforms PICM default changes from 1 to 0. Fix comments about PICM==0 used to indicate use of i8259 PIC for interrupt delivery. Change-Id: I525ef8353514ec32941c4d0c37cab38aa320cb20 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49905 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11sb,soc/intel: Drop OSYS from GNVSKyösti Mälkki
The value should be set by OSPM using some combination of _OSI() queris in the \_SB._INI() method. To maintain previous behaviour with this commit, boards where GNVS osys initialisation was removed now do the same in ASL. Change-Id: Id4957b12a72fbf7fa988e7ff039e47abcc072e1c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49353 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11mainboards: Drop PWRS from GNVSKyösti Mälkki
Initialize variable to 1 to indicate AC power supply. If platform has EC it will set this correctly based on whether plugged on the charger or not. Change-Id: I3f834cf7563b9e512fcab34cdb7a27a9f0fd31c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49352 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10src: Remove unused <boot_device.h>Elyes HAOUAS
Change-Id: Idbb4d72e1ba620f71e8bf882d434c103cb422615 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50201 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-08soc/intel: Drop CID1 from GNVSKyösti Mälkki
The only reference to CID1 is in common/acpi/wifi.asl and only two braswell boards include it. Everywhere else the value in GNVS was unused. Change-Id: I09ea756fb3743e33d1e221f0a0df3a6fdc3fc3ba Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-07acpi: Fix BERT size_t printf format errorBenjamin Doron
Fix compilation on GCC 10.2.1 and address the underlying issue. The printf format specifier for a size_t type is z. Change-Id: Ieb1db6c0c3eb4947bd3617e418bac238b70ec08f Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-06intel: Rename config FSP_USES_MP_SERVICES_PPI to MP_SERVICES_PPIFurquan Shaikh
This change renames config FSP_USES_MP_SERVICES_PPI to MP_SERVICES_PPI in preparation to allow V1 and V2 versions of MP services PPI. TEST=Verified that timeless build for brya, volteer, icelake_rvp, elkhartlake_crb and waddledee shows no change in generated coreboot.rom Change-Id: I04acf1bc3a3739b31d6e9d01b6aa97542378754f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50275 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-06intel: Drop FSP_PEIM_TO_PEIM_INTERFACEFurquan Shaikh
This change drops the config FSP_PEIM_TO_PEIM_INTERFACE. FSP_PEIM_TO_PEIM_INTERFACE is used for: * Auto-selecting FSP_USES_MP_SERVICES_PPI * Including src/drivers/intel/fsp2_0/ppi/Kconfig * Adding ppi to subdirs-y * Setting USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI to y and is selected by SoCs that want to enable MP PPI services. Instead of using the indirect path of selecting MP PPI services, this change allows SoC to select FSP_USES_MP_SERVICES_PPI directly. The above uses are handled as follows: * Auto-selecting FSP_USES_MP_SERVICES_PPI --> This is handled by SoC selection of FSP_USES_MP_SERVICES_PPI. * Including src/drivers/intel/fsp2_0/ppi/Kconfig --> The guard isn't really required. The Kconfig options in this file don't present user prompts and don't really need to be guarded. * Adding ppi to subdirs-y --> Makefile under ppi/ already has conditional inclusion of files and does not require a top-level conditional. * Setting USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI to y --> This is set to y if FSP_USES_MP_SERVICES_PPI is selected by SoC. TEST=Verified that timeless build for brya, volteer, icelake_rvp, elkhartlake_crb and waddledee shows no change in generated coreboot.rom Change-Id: I0664f09d85f5be372d19925d47034c76aeeef2ae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50274 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04acpi: Add support for reporting CrashLog in BERT tableFrancois Toguo
Crash Data are collected and sent to the OS via the ACPI BERT. BUG=None TEST=Built, and BERT successfully generated in the crashLog flow. Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com> Change-Id: I00e390d735d61beac2e89a726e39119d9b06b3df Signed-off-by: Nikunj A. Dadhania <nikunj.dadhania@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-04src: Remove unused <bootstate.h>Elyes HAOUAS
Change-Id: I0d2ab4144970184f46e1d0e7a2464e94fa38aa63 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2021-02-03pci_ids/intel: Add missing CFL-S GT1 IGD IDsNico Huber
Change-Id: I372b6b2d602dfe116d5791bb6a6653454523b42b Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Timofey Komarov <happycorsair@yandex.ru>
2021-02-03pci_ids/intel: Correct 0x3e96, it's a CFL-S partNico Huber
Change-Id: Ibdddb3309f862f52c578e91ba3dc310dff8f70bc Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Timofey Komarov <happycorsair@yandex.ru> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-03soc/intel: Fix compilation on x86_64Patrick Rudolph
Change-Id: I18a0c18fe1c64611f95bc423916447c89585db9f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-02-01soc/intel/common/sata: Add support for Cannon Lake SATA (HALO)Erik van den Bogaert
Add device ID of Cannon Lake PCH-H Mobile HALO SATA controller in supported device table. Bug=N/A TEST=Build of Intel Coffeelake H SO-DIMM DDR4 RVP11 successfully completed Change-Id: Ie1c2aa8273a53c47d7b3571394bcd85b59ab1142 Signed-off-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-02-01soc/intel/*: Get rid of custom microcode cachingPatrick Rudolph
Get rid of custom microcode caching in MPinit and SGX code and use the caching introduced in intel_microcode_find() instead. Change-Id: If3ccd4dcff221c88839ffeafa812f4c38cede63f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01drivers/intel/fsp2_0: Use coreboot postcar with FSP-TArthur Heymans
Allow platforms to use the coreboot postcar code instead of calling into FSP-M TempRamExit API. There are several reasons to do this: - Tearing down CAR is easy. - Allows having control over MTRR's and caching in general. - The MTRR's set up in postcar be it by coreboot or FSP-M are overwritten later on during CPU init so it does not matter. - Avoids having to find a CBFS file before cbmem is up (this causes problems with cbfs_mcache) Change-Id: I6cf10c7580f3183bfee1cd3c827901cbcf695db7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48466 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30soc/intel: Replace `SA_PCIEX_LENGTH` Kconfig optionsAngel Pons
Use the existing `MMCONF_BUS_NUMBER` and `MMCONF_LENGTH` symbols. Change-Id: I88dcc0d5845198f668c6604c45fd869617168231 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-30soc/amd,intel: Drop leftover GNVS includesKyösti Mälkki
Change-Id: Ia55d53a9a40846db335aabbe4df8e87f6172f712 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-30soc/intel/common/block: Create PCIE related macrosSubrata Banik
Add generic PCIE RP related macros for SoC layer to use. Change-Id: I84d02daded5cfe11120f099dc80c00ac0ec795f1 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-29soc/intel: Remove duplicate call to acpi_wake_source()Kyösti Mälkki
With SOC_INTEL_COMMON_BLOCK_ACPI=y the call was made twice, possibly in the order: common/block/acpi.c: acpi_wake_source() common/acpi_wake_source.c: acpi_wake_source() In this order later call would reset pm1i and gpei in GNVS. Remove the implementation in block/acpi.c and rename existing acpi_wake_source.c to block/acpi_wake_source.c. Change-Id: I74fdae63111e3ea09000d888a918ebe70d711801 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-29device/Kconfig: Declare MMCONF symbols' type onceAngel Pons
Only specify the type of MMCONF_BASE_ADDRESS and MMCONF_BUS_NUMBER once. Change-Id: Iacd2ed0dae5f1fb6b309124da53b3fa0eef32693 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50032 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28soc/intel: Remove selection of ME_REGION_ALLOW_CPU_READ_ACCESSSridhar Siricilla
The patch removes selection of ME_REGION_ALLOW_CPU_READ_ACCESS config in the SOC_INTEL_CSE_LITE_SKU Kconfig definition since the ME_REGION_ALLOW_CPU_READ_ACCESS Kconfig selection is done based on the SOC_INTEL_CSE_LITE_SKU Kconfig in the southbridge/intel/common/firmware/Kconfig. TEST=Verified build for JSL Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I9969cce0d433657dd27bab71c132356fb28a35c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50012 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28ACPI: Separate ChromeOS NVS in ASLKyösti Mälkki
For builds with MAINBOARD_HAS_CHROMEOS=y but CHROMEOS=n, there is reduced dsdt.aml size and reduced GNVS allocation from cbmem. More importantly, it's less error-prone when the OperationRegion size is not hard-coded inside the .asl files. Change-Id: I54b0d63a41561f9a5d9ebde77967e6d21ee014cd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49477 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28ACPI: Declare GNVS variables globallyKyösti Mälkki
There is a common place where acpigen generates these, so the declarations for the OperationRegions should be centralized too. Change-Id: I772492ca9e651b60244c565d1e926dc2ad33cfd8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49795 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28soc/intel: Refactor acpi_wake_source()Kyösti Mälkki
Change-Id: I44cb499260fdd0ea37308909a24cdf5ca1afa025 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49879 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28soc/intel: Refactor fill_acpi_wake()Kyösti Mälkki
Change-Id: I7fcc2b36cfe57adf8ae3a6acf8b54e19504202a5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49878 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-26soc/intel: Move c-state resource defineMarc Jones
De-duplicate the MWAIT_RES define. Move it to intel/common/block. Change-Id: I43903e4f02a549f53101e79f6febd42f2e54f98f Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49802 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25sb,soc/intel: Remove no-op APMC for C-state and P-stateKyösti Mälkki
Change-Id: I3c1aa7f68eb03f04ddb9c1a5e960e3e2050a029c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49250 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25cpu/x86/smm: Use common APMC loggingKyösti Mälkki
Unify the debug messages on raised SMIs. Change-Id: I34eeb41d929bfb18730ac821a63bde95ef9a0b3e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49248 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25soc/intel/{skl,cnl,xsp,icl,tgl,ehl,adl,jsl}: use common LPC mirroringMichael Niewöhner
Drop the old, redundant code for mirroring LPC registers to DMI and make use of the new common code. Select the new Kconfig option for LPC DMI mirroring by the option SOC_INTEL_COMMON_PCH_BASE, which is selected by platforms starting with SPT, except APL and Xeon-SP. For Xeon-SP, select DMI and the new Kconfig directly. APL, even though it's younger than SPT, does not need mirroring. Test: Set LGMR address by calling `lpc_open_mmio_window` and check that both the PCI cfg and DMI LGMR register get written correctly. Tested successfully on clevo/cml-u. Change-Id: Ibd834f1474d986646bcebb754a17db97831a651f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49593 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-25soc/intel/lpc_lib: mirror LPC registers to DMI when requiredMichael Niewöhner
Starting with SPT, LPC registers IOD, IOE, LGIR* and LGMR need to be mirrored to their corresponding DMI registers. Add the required writes to DMI registers, where the PCI config registers get written. This is already done in soc code for IOD, IOE and LGIR* by mirroring the registers later, during PCH init. Also the code mostly matches accross the platforms. This common implementation will avoid delayed mirroring of the registers and also deduplicate the code. This change also adds a new Kconfig that will be selected by platforms requiring mirroring of LPC IO/MMIO registers to their corresponding DMI registers. For making use of this common code, the redundant soc code needs to be dropped and the newly introduced Kconfig option has to be selected. This is done in the follow-up change. Change-Id: I39f3bf4c486a1bbc112b2b453381de6da4bbac4d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-25soc/intel/common: Add support for populating meminit dataFurquan Shaikh
This change adds support for a common block memory driver that can be used for performing the required operations to read SPD data for different memory channel DIMMs. This data can then be used by the SoC code to populate different memory related UPDs. Most recent Intel platforms follow a similar pattern for configuring FSP-M UPDs for initializing memory. These platforms use one of the following topologies: 1. Memory down 2. DIMM modules 3. Mixed Thus, SPD data is either obtained from CBFS (for memory down topology) or from on-module EEPROM (for DIMM modules). This SPD data read from CBFS or EEPROM is then passed into FSP-M using SPD UPDs for different channels/DIMMs as per the memory organization. Similarly, DQ/DQS configuration is accepted from mainboard and passed into FSP-M using UPDs as per the FSP-M/MRC organization of memory channels. Different memory technologies on a platform support physical channels of different widths. Since the data bus width is fixed for a platform, the number of physical channels is determined by data bus width / physical channel width. The number of physical channels are different depending upon the size of physical channel supported by the memory technology. FSP-M for a platform uses the same set of UPDs for different memory technologies and aims at providing maximum flexibility. Thus, the platform code needs to format mainboard inputs for DQ, DQS and SPD into the UPDs appropriately as per the memory technology used by the board. Example: DDR4 on TGL supports 2 physical channels each 64-bit wide. However, FSP-M UPDs assume channels 16-bit wide. Thus, FSP-M provides 16 UPDs for SPDs (considering 2 DIMMs per channel and 8 channels with each channel 16-bit wide). Hence, for DDR4, only the SPD UPDs for MRC channel 0 and 4 are supposed to be used. This common driver allows the SoC to define the attributes of the platform: 1. DIMMS_PER_CHANNEL: Maximum DIMMs that are supported per channel by any memory technology on the platform 2. DATA_BUS_WIDTH: Width of the data bus. 3. MRC_CHANNEL_WIDTH: Width of the channel as used by the MRC to define UPDs. In addition to this, the SoC can define different attributes of each memory technology supported by the platform using `struct soc_mem_cfg`: 1. Number of physical channels 2. Physical channel to MRC channel mapping 3. Masks for memory down topologies Using the above information about different memory technologies supported by the platform and the mainboard configuration for SPD, the common block memory driver reads SPD data and provides pointers to this data for each dimm within each channel back to the SoC code. SoC code can then use this information to configure FSP-M UPDs accordingly. In addition to that, the common block driver also returns information about how the channels are populated so that the SoC code can use this information to expose DQ/DQS information in FSP-M UPDs. This driver aims at minimizing the effort required for supporting different memory technologies on any new Intel SoC by reducing per-SoC effort to a table of configurations rather than having to implement similar logic for each SoC. BUG=b:172978729 Change-Id: I256747f0ffc49fb326cd8bc54a6a7b493af139c0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49040 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24soc/intel/lpc_lib: drop dead codeMichael Niewöhner
Change-Id: I7cf5f97c3229fe6a72d70a36e8cff49ff3cf611b Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-23ACPI: Add helpers for CBMEM_ID_POWER_STATEKyösti Mälkki
Create uniform logging for the (unlikely) case of a CBMEM entry disappearing. Change-Id: I7c5414a03d869423c8ae5192a990fde5f9582f2d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-23soc/intel/apl: drop LPC pad configuration codeMichael Niewöhner
Drop LPC pad configuration code since all boards now do pad configuration on their own. The comment about LPC_CLKRUNB when using eSPI is moved to `Documentation/getting_started/gpio.md`. Change-Id: I710d6aee8c3b2c8282cd321cd0688b9b26abea07 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49410 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-22soc/intel/commmon: Include Alder Lake device IDsVarshit Pandya
Add Alder Lake M specific CPU, System AGent, PCH (Alder Point aka ADP), IGD device IDs. Document Number: 619501, 626817 Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com> Change-Id: Ib13fe229f9e65eae8967aa20e28e29ac5c319265 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49629 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21soc/intel/common/pcie_rp.h: Fix comment styleFurquan Shaikh
This change updates pcie_rp.h to reflow the comment blocks to fit within 80 columns to match the original style of the file. This addresses comment received on CB:49370 (https://review.coreboot.org/c/coreboot/+/49370/comment/0f3fe10d_4e218b5f/). Change-Id: I565ad602e0e3a2ee09e8345479d82e2ce0a31fd0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-01-21soc/intel/common/graphics: Add new Kconfig SOC_INTEL_DISABLE_IGDSubrata Banik
This SOC_INTEL_DISABLE_IGD Kconfig will allow to skip IGD initialization using FSP GOP and eventually disable the IGD. TEST=Able to get depthcharge pre-OS splash screen when mainboard user selects SOC_INTEL_DISABLE_IGD with below HW/FW/SW configuration: HW: ADLRVP + AMD Radeon RX 5700 PCI-E DGPU FW: coreboot with depthcharge as payload for ADLRVP and OpRom for AMD PCI-E DGPU SW: Chrome OS RC10 release Change-Id: I465541cb45c9022d53a5beb3fff1f80660c357c9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-20soc/intel: fix indentation in intelblocks/lpc_lib.hMichael Niewöhner
Change-Id: I28be6091097f713472d5ca3b8b0921ee71238cf0 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-01-20soc/intel/*: drop broken LPC mmio codeMichael Niewöhner
The code for setting the LPC generic memory range uses an array of fixed address ranges not needing explicit decoding, to decide if the address needs to be written to the LGMR register. Most platforms only mistakenly add the PCH reserved mmio range, that is not decoded generally, effectively breaking the mechanism. Only APL uses the array correctly. That code, in it's current state, does not work (except for APL) and currently, there is not a single user. Thus, drop it before people start using it. Change-Id: I723415fedd1b1d95c502badf7b0510a1338b11ac Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-20ACPI GNVS: Drop most dev_count_cpu()Kyösti Mälkki
Only amd/picasso and amd/stoneyridge have reference to PCNT and that could be replaced with acpigen. Remove the PCNT name from GNVS OperationRegion elsewhere. Change-Id: I7dd45a840b3585fd24c31fd923b991c34ab4d783 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-07 21:32:55 +0000