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2022-09-16soc/intel/common: Update comment on HFSTS1.spi_protection_modeSridhar Siricilla
The patch updates comment on HFSTS1.spi_protection_mode. The spi_protection_mode indicates SPI protection status as well as EOM status (in a single staged EOM flow). Starting from TGL platform, staged EOM flow is introduced. In this flow, spi_protection_mode alone doesn't indicate the EOM status. For information on EOM status, please refer secton# 3.6.1 in doc# 612229. TEST=Build code for Gimble Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I19df5cfaa6d49963bbfb3f8bc692d847e58c4420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-09-16Revert "drivers/wifi: Move MTL Magnetar CNVi DIDs from SoC to generic driver"Subrata Banik
This reverts commit 510a55d4eeaeb32047c17328ef238b55b89e7296. Reason for revert: Observed `missing read resource` issue for cnvi device BUG=b:244687646 TEST=No error seen in AP log while booting Google/rex Without this patch: [SPEW ] PCI: 00:14.3 read_resources bus 0 link: 0 [ERROR] GENERIC: 0.0 missing read_resources [SPEW ] PCI: 00:14.3 read_resources bus 0 link: 0 done With this patch: [SPEW ] PCI: 00:14.3 read_resources bus 0 link: 0 [SPEW ] PCI: 00:14.3 read_resources bus 0 link: 0 done Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1e881313729f1088cffa7c161722ee79bb9acc49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67566 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-09-15soc/intel/skylake: Assign device ops in chipset devicetreeNico Huber
Some PCI IDs were missing, and at least one (SPT's fast SPI device in a generic SPI driver) was wrong. Hence, this patch actually changes behavior depending on the devices actually present in a machine. In this patch the Skylake devicetree is written in a single-line style. Alternative, the device operations could be put on a separate line, e.g. device pci 00.0 alias system_agent on ops systemagent_ops end Tested on Kontron/bSL6. Notable in the log diff is that the CSE and SATA drivers are hooked up now. Change-Id: I8635fc53ca617b029d6fe1845eaef6c5c749db82 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-09-14timer: Change timer util functions to 64-bitRob Barnes
Since mono_time is now 64-bit, the utility functions interfacing with mono_time should also be 64-bit so precision isn't lost. Fixed build errors related to printing the now int64_t result of stopwatch_duration_[m|u]secs in various places. BUG=b:237082996 BRANCH=All TEST=Boot dewatt Change-Id: I169588f5e14285557f2d03270f58f4c07c0154d5 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-09-08soc/intel/common/smbus: Add missing ID for GLKSean Rhodes
PCI ID taken from Intel doc #569262. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I31d4b7edf3288794c86a6d2b78acdc4cf0ac611f Reviewed-on: https://review.coreboot.org/c/coreboot/+/67405 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-08soc/intel/commmon/fast_spi: Add missing ID for GLKSean Rhodes
PCI ID taken from Intel doc #569262. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I5812e536f3e1c49a272a0b337cc69f3d8f30677f Reviewed-on: https://review.coreboot.org/c/coreboot/+/67402 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-06src/soc/intel: remove force-included header compiler.h from fileMartin Roth
The header file `compiler.h` is automatically included in the build by the top level makefile using the command: `-include $(src)/commonlib/bsd/include/commonlib/bsd/compiler.h`. Similar to `config.h`, 'kconfig.h`, and 'rules.h`, this file does not need to be included manually, so remove it. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I5d3eb3f5e5f940910b2d45e0a2ae508e5ce91609 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-06src: remove force-included header rules.h from individual filesMartin Roth
The header file `rules.h` is automatically included in the build by the top level makefile using the command: `-include src/soc/intel/common/block/scs/early_mmc.c`. Similar to `config.h` and 'kconfig.h`, this file does not need to be included manually, so remove it. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I23a1876b4b671d8565cf9b391d3babf800c074db Reviewed-on: https://review.coreboot.org/c/coreboot/+/67348 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-03soc/intel: Add SI_DESC region to GSCVD rangesJulius Werner
Intel platforms have soft straps stored in the SI_DESC FMAP section which can alter boot behavior and may open up a security risk if they can be modified by an attacker. This patch adds the SI_DESC region to the list of ranges covered by GSC verification (CONFIG_VBOOT_GSCVD). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I0f1b297e207d3c6152bf99ec5a5b0983f01b2d0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66346 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-02cbfs/vboot: Adapt to new vb2_digest APIJulius Werner
CL:3825558 changes all vb2_digest and vb2_hash functions to take a new hwcrypto_allowed argument, to potentially let them try to call the vb2ex_hwcrypto API for hash calculation. This change will open hardware crypto acceleration up to all hash calculations in coreboot (most notably CBFS verification). As part of this change, the vb2_digest_buffer() function has been removed, so replace existing instances in coreboot with the newer vb2_hash_calculate() API. Due to the circular dependency of these changes with vboot, this patch also needs to update the vboot submodule: Updating from commit id 18cb85b5: 2load_kernel.c: Expose load kernel as vb2_api to commit id b827ddb9: tests: Ensure auxfw sync runs after EC sync This brings in 15 new commits. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I287d8dac3c49ad7ea3e18a015874ce8d610ec67e Reviewed-on: https://review.coreboot.org/c/coreboot/+/66561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2022-09-02soc/intel/cmn/graphics: Use pci_dev_request_bus_master for BM enablingSubrata Banik
Enabling Bus Master isn't required by the hardware, so we shouldn't need to enable it at all. However, some payloads do not set this bit before attempting DMA transfers, which results in functionality failure. For example: in this case, unable to see the developer screen in Depthcharge. In the prior IA SoC platform, FSP/GFX PEIM does the BM enabling for the IGD BAR resources but starting with the MTL platform, it fails to do so resulting into inability to see the Pre-OS display. BUG=b:243919230 ([Rex] Unable to see Pre-OS display although GFX PEIM Display Init is successful during AP boot) TEST=Able to see the developer screen with eDP/HDMI while booting the Google/Rex. Also, this change doesn't impact the previous platforms (ADL, TGL, CML etc.) where the BM is default enabled. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9ad9eee8379b7ea1e50224e3fabb347e5f14c25b Reviewed-on: https://review.coreboot.org/c/coreboot/+/67273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-08-30soc/intel/cmn/block/acpi: Add new GPIO ASL MethodTim Wawrzynczak
Ths new Method, GSCI, allows control over whether or not IRQs are routed as SCI#s for the given GPIO. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ic61caaf77d2c6e295e67a1501544e8b8fc6f3b6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/66813 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-30soc/intel/cmn/block/acpi: Modify GPIO Methods to use bitfieldsTim Wawrzynczak
IMHO, using bitfields directly in the Field declaration makes the ASL code more readable then directly manipulating the entire 32-bit dword. TEST=ACPI code using several of these Methods still works (google/agah dGPU ACPI code) Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I9909700022d8b55db3f5208010bdff11ddaf4e7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66812 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-26soc/intel/p2sb: Refactor `p2sb_execute_sideband_access` functionSubrata Banik
This patch refactors p2sb_execute_sideband_access() to be able to handle SBI operations in both SMM and non-SMM scenarios. Prior to FSP-S operation being done, the IOE P2SB device will be visible on the PCI bus hence, performing the SBI operation using IOE P2SB doesn't involve unhide/hide operation. Post FSP-S, the IOE P2SB device is hidden. Additionally, SBI operations can't be performed as is. The only possible way to send SBI is inside SMM mode and to do that, coreboot needs to unhide the P2SB device prior to sending the SBI and hide it post sending SBI. As a result, the p2sb_execute_sideband_access() function has been refactored to manage these cases seamlessly without users of the p2sb_execute_sideband_access() actually being bothered about the calling mode. BUG=b:239806774 TEST=Able to perform p2sb_execute_sideband_access() function call in both SMM and non-SMM mode without any hang/die. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iafebd5190deb50fd95382f17bf0248fcbfb23cb8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-24soc/intel/common/block: Drop empty smm.hAngel Pons
This file has nothing useful. Get rid of it. Change-Id: Id2a42005d3b4b5161079c9ff48867cfc6fb0413d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-08-24soc/intel/common/gpio: Support 4 bits GPIO pad mode configurationJamie Ryu
Intel GPIO pad supports 4 bits pad mode, PAD_CFG_DW0[13:10] for pins that native function 8 to 15 is assigned. This adds native function definitions from NF8 to NF15 and updates PAD_CFG0_MODE_MASK to support 4 bits pad mode configuration. Since PAD_CFG_DW0[16:13] is reserved for pins that NF8 or higher is not assigned, this change would not cause an issue but Kconfig option is added to minimize an impact and support 4 bits pad mode configuration. BUG=b:239690757 TEST=build and verify pad mode configuration with Meteor Lake mtlrvp Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: Iefd2daa92a86402f2154de2a013ea30f95d98108 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-08-22soc/intel/cmn/cpu: API to set TME core activationSubrata Banik
This patch implements API to program TME core activation MSR 0x9FF. Write zero to TME core activate MSR will translate the TME_ACTIVATE[MK_TME_KEYID_BITS] value into PMH mask register. Note: TME_ACTIVATE[MK_TME_KEYID_BITS] = MSR 0x982 Bits[32-35] TEST=Able to build and boot Google/Redrix. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I48cf8e255b294828ac683ab96eb61ad86578e852 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-21soc/intel/common/block/cpu: API to check if TME is supportedSubrata Banik
As per the Alder Lake FAS coreboot shall detect the existence of TME feature by running the CPUID instruction: CPUID leaf 7/sub-leaf 0 Return Value in ECX [bit 13]=1 If TME is supported then only access to TME MSRs are allowed otherwise accessing those MSRs would result in GP#. TEST=Able to detect the existence of TME feature across different Alder Lake and Meteor Lake CPU SKUs. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ibd4fcf15a66d27748ac7fbb52b18d7264b901cd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66749 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-21soc/intel: Unravel `INTEL_TME` Kconfig optionAngel Pons
The `INTEL_TME` Kconfig option has a prompt, which means it is meant to be user-configurable. However, it has been selected from Alder Lake and Meteor Lake Kconfig, so `INTEL_TME` cannot be disabled on them. Replace the `select INTEL_TME` statements with default values in order for this option to be user-configurable on all platforms that support it. Change-Id: Ib37c108fcc1004840b82be18fd23c340a68ca748 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66756 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-21intel/systemagent: Align debug outputNico Huber
Output should be easier to read as a table. Change-Id: I32e3e0aab5afd25c0b004d18f64de76445d9a0ed Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-08-17soc/intel/common: Update the comments for CSE RX and TX functionsSridhar Siricilla
The patch updates the comments on return values and heci_reset() triggering during error scenarios of heci_receive() and heci_send() functions to reflect the current implementation. Test=Build the code for Gimble Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I6c6c3312602c772147cb315db9ea1753d84a0fb3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-16soc/intel/common/cpu: Remove the address-of (`&`) operator usageSubrata Banik
This patch drops explicit usage of the address-of operator ('&') while passing the function pointer (argument 0) to the `mp_run_on_all_cpus` API. Note: It's just cosmetic change without any real difference in the operation. TEST=Able to build and boot Google/Kano where CPU feature programming is successful on all logical processors. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I2c77959a76d2240ad1bfb7a9d7b9db7e8aee42f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66685 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-14soc/intel/common/block/cse: Tidy up table in commentAngel Pons
Adjust an ASCII art table so that it looks good: consistent padding and aligned table borders. Change-Id: I26196f969406e03f320256b0c3a337282f636914 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66707 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-08-13src/mb: Update unlicensable files with the CC-PDDC SPDX IDMartin Roth
These files contain no creative content, and therefore have no copyright. This effectively means that they are in the public domain. This commit updates the unlicensable empty (and effectively empty) files with the CC-PDDX identifier for license compliance scanning. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I0b76921a32e482b6aed154dddaba368f29ac2207 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66497 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-12Fix Alder Lake and Raptor Lake Device ID'sMaximilian Brune
- ADP_P_* -> RPP_S_* (got mixed up I guess) - Remove duplicates of ADP_S_ESPI_* - Add infix _ESPI_ to all ADP_S device ID's Document: 619362 Change-Id: Ic18ecbd420fc598f0ef6e3cf38e987ac3ae6067e Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66629 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-12Add missing ADL-S device identificationMaximilian Brune
R680E, Q670E, H610E are the ADL-S IoT variants TEST=Boot ADL-S RVP DDR5 and see silicon info is reported as PCH: AlderLake-S R680E Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I1804994b4b72f0484eabb15323736679d2668078 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-12soc/intel/common: Delete the TBT authenticaton functionJohn Zhao
Delete the Thunderbolt authentication function ioe_tcss_valid_tbt_auth from the common block. Meteor Lake Platform will implement it. BUG=b:213574324 TEST=Built coreboot image successfully. Change-Id: I97a289faa6351fe562f91d8478b72c9403ce88cb Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-12soc/intel/common: Ignore prefetch PCI attribute for IGD BAR0Wonkyu Kim
From Meteorlake, IGD BAR0(GTTMMADR) is changed to 64bit prefetchable. Due to the prefetchable attribute, resource allocation for IGD BAR0 is assigned WC memory and it causes kernel driver failure. For avoiding kernel driver failure, ignore prefetch PCI attribute for IGD BAR0 to assign UC memory. We're working on publishing below information. - IGD BAR0(GTTMMADR) is changed to 64bit prefetchable BAR - GTTMMADDR BAR should be always mapped as UC memory although marked Pre-fetchable. BUG=b:241746156 TEST=boot to OS and check guc driver loading successful Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I76d816d51f32f99c5ebcca54f13ec6d4ba77bba5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66403 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-03soc/soc/intel: Add UFS device with ref-clk-freq propertyMeera Ravindranath
UFS storage devices require the bRefClkFreq attribute to be set to operate correctly in high speed mode. The correct value is determined by what the SoC / board supports. For the ADL UFS controller, it is 19.2 MHz. a) Introduce a new ACPI property "ref-clk-freq". b) Add support to configure this property using an SoC Kconfig. Kernel patch: https://web.archive.org/web/20220801060732/https://lore.kernel.org/all/ 20220715210230.1.I365d113d275117dee8fd055ce4fc7e6aebd0bce9@changeid/ BUG=b:238262674 TEST=Build,boot Nirwen and dump SSDT entries and check that the kernel correctly parses ref-clk-freq as 19.2 MHz. Scope (\_SB.PCI0) { Device (UFS) { Name (_ADR, 0x0000000000120007) // _ADR: Address Name (_DDN, "UFS Controller") // _DDN: DOS Device Name Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, Package (0x01) { Package (0x02) { "ref-clk-freq", 0x0124F800 } } }) } } Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Signed-off-by: Reka Norman <rekanorman@chromium.org> Change-Id: I80c338a8a61f161b0feb6c5a3ca00cf5e0cfb36c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-29intel/pmclib: Avoid PMC ABASE read of SLP_TYP and STATUS in ramstageHarsha B R
The patch updates platform_is_resuming() API such that platform resume state is determined from the saved state (CBMEM) instead of checking PMC registers (PM1_STS & PM1_CNT) as they are getting cleared (before/early) ramstage. coreboot sends DISCONNECT IPC command which times out during resume (S3) if system has servoV4 connected on port0. The issue occurs only during the first cycle of resume (S3) test cycle after cold boot due to side effect of platform_is_resuming() API that is not determining the resume (S3) state correctly in ramstage. PM1_STS and PM1_CNT register gets cleared at the start of ramstage. platform_is_resuming() function was checks the cleared register value and fails the condition of resume (S3) resulting in sending DISCONNECT IPC command. Checking the platform resume state from the CBMEM saved state using acpe_get_sleep_type() function helps cross verify the system previous state at the later part of ramstage. localhost ~ # cbmem -c | grep ERROR [ERROR] EC returned error result code 3 [ERROR] PMC IPC timeout after 1000 ms [ERROR] PMC IPC command 0x200a7 failed [ERROR] pmc_send_ipc_cmd failed [ERROR] Failed to setup port:0 to initial state [ERROR] PMC IPC timeout after 1000 ms [ERROR] PMC IPC command 0x200a7 failed [ERROR] pmc_send_ipc_cmd failed [ERROR] Failed to setup port:1 to initial state [ERROR] GENERIC: 0.0 missing read_resources [ERROR] PMC IPC timeout after 1000 ms [ERROR] PMC IPC command 0xd0 failed [ERROR] PMC: Failed sending PCI Enumeration Done Command BUG=b:227289581 TEST=Verified system boots to OS and verified below tests on Redrix (ADL-P) and Nivviks (ADL-N) 1. coreboot doesn't send the DISCONNECT during S3 resume 2. suspend S3 passes with both suzyq and servoV4 connected 3. After S3 resume, system detects the pen drive with Superspeed 4. After system resumes from S3, hot-plug the pen drive, system detects the pen drive Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I353ab49073bc4b5288943e19a75efa04bd809227 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66126 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-29soc/intel/common/sata: Add APL and GLK SATA PCI IDsSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I0ae8c6624b79ce6c269244bd1435900d4d7f997a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-07-28soc/intel/gpio: Add new macro for GPP PAD reset type as `Global Reset`Subrata Banik
This patch introduces a new macro for GPP PAD reset type as `Global Reset` as documented in Alder Lake EDS doc 630603. BUG=b:213293047 TEST=Able to build Google/Kano with this change. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I39428911babc393dd10750801522a00d0b26d3e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-25soc/intel/gpio: Update GPIO Lock configuration recommendationSubrata Banik
This patch updates the GPIO lock configuration recommendation kconfig string to ensure the SoC user can select the correct config as applicable for the SoC. Note: From MTL onwards GPIO lock config can be performed using PCR write (MMIO write) and the GPIO team has confirmed this. BUG=b:213596994 TEST=Able to fix below GPIO lock config error msg on MTL with `SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_PCR` kconfig enabled. [INFO ] Locking pad configuration using SBI [INFO ] gpio_pad_config_lock_using_sbi: Locking pad 73 configuration [ERROR] SBI Failure: Transaction Status = 1 [ERROR] Failed to lock GPIO PAD, response = 1 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Icab1e4849b8e08ee1c695c924599f1513774178f Reviewed-on: https://review.coreboot.org/c/coreboot/+/66113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-24intel/common/block/ipu: Add MTL IPU device idWonkyu Kim
TEST=Build mtlrvp and check IPU0 ACPI ojbect from ssdt Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ib5c3d455d272af0e753c775a5fd3f19851b7937d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66056 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-20treewide: Remove unused <cpu/x86/msr.h>Elyes Haouas
Change-Id: I187c2482dd82c6c6d1fe1cbda71710ae1a2f54ad Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-20soc/intel/cmn/pch/lockdown: Guard gpmr_lockdown_cfgSean Rhodes
Guard gpmr_lockdown_cfg with SOC_INTEL_COMMON_BLOCK_GPMR so it doesn't run on platforms that don't select this. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Iab5bbd399c3a654dcb95eaa8fce683a50c7322f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65227 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-07-20soc/intel/common/pch: Decouple CLIENT from BASEAngel Pons
In preparation to add a third option, have "Client" platforms select a dedicated Kconfig option instead of the common "_BASE" option. Rewrite the help texts to clarify what "Client" and "Server" mean, because the terms refer to the type of silicon and not to the market segment. Some uniprocessor (single-socket) servers are actually client platforms and there are some multi-socket workstations based on a server platform. Change-Id: I646729d709f60ca2b5e74df18c2b4e52f9b10e6b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-07-14soc/intel/common: Introduce SOC_INTEL_COMPLIANCE_TEST_MODEJeremy Compostella
This config can be used to make coreboot configure the hardware to meet compliance tests requirements. SoCs which support compliance testing features should set the SOC_INTEL_SUPPORTS_COMPLIANCE_TEST_MODE flag. BUG=b:235863379 TEST=Successful compilation Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: Iec760ae89e2b892ef45e6750e823ab5a8609d0fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/65091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-11soc/intel/common/block/pmc/pmclib: Use same loglevel as print_num_status_bitsPatrick Rudolph
Use same log level as print_num_status_bits to make sure the status bits are properly prefix and the newline is added. Change-Id: Ib33798eec7cba601d0d49646c5fc429de5268417 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65715 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-07-09*/fsp/exit_car: Push stack address into %espArthur Heymans
Fixes: 5315e96abf ("arch/x86/postcar: Use a separate stack for C execution") Resolves: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/ thread/TGIWAKZKELJRAEMKJNYRJ55MX2CXYNCV/ Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/ thread/2JC3GNJSGXUD6DRVUY7O2O3W6OM3E2MY/ 5315e96abf broke platforms using FSP-M to tear down CAR. It was pushing the value at '_estack' into %esp rather than the address '_estack'. Change-Id: Ie1fc70bd60fe3a2519ffb71625a35630fa732ff6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65716 Reviewed-by: Patrick Georgi <patrick@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-07-08soc/intel/common/pch: Fix incorrect GPE numberReka Norman
BUG=None TEST=None Change-Id: I7a4081f0f57e0faa968ad142debdc40a9e26dc9b Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65690 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-07soc/intel/common/graphics: Add another Meteor Lake device IDWonkyu Kim
Add 0x7d55 as another ID for Meteor Lake graphics controllers. TEST=Boot with MTL silicon to check coreboot log for DID2 Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Iea01f6d4f2469fc0eeac73a3f1c4b9af1f39463c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2022-07-06soc/intel/common: Update the comment on CSE Region layoutSridhar Siricilla
The comment indicates CSE's data partition is placed after BP2. But, it was place after BP1.So, the patch updates the comment to reflect the CSE Region layout correctly. TEST=Build the code for Brya and didn't notice any compilation errors Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ic871e2e395de17157f4f526064a26bfad538707f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-07-06common/intel/cse: Add function to perform CSE FW update in ramstageKrishna P Bhat D
When compressed ME RW blobs are used for CSE FW update, it has to be loaded into memory to decompress. So perform CSE FW update in ramstage. Alder Lake-N based nissa boards use compressed ME RW blobs to save on SPI flash size. Enable CSE FW update in ramstage. BRANCH=firmware-brya-14505.B TEST=Perform CSE FW update on nivviks and verify upgrade/downgrade works. Change-Id: Ide9471146d186dca11fb020e5006eeaa01442669 Signed-off-by: Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-05nb,soc/intel: Handle upper RAM boundaryKyösti Mälkki
Change-Id: I2d99523647dfb43265db8f2701b525afd1870fc5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-07-04treewide: Unify Google brandingJon Murphy
Branding changes to unify and update Chrome OS to ChromeOS (removing the space). This CL also includes changing Chromium OS to ChromiumOS as well. BUG=None TEST=N/A Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-06-30soc/intel/common: Compile debug_feature in ramstage to fix build errorKrishna P Bhat D
In ADL-N, cse_fw_sync is done in ramstage. Compile debug_feature.c in ramstage to fix build error. BRANCH=firmware-brya-14505.B Change-Id: I0118b024fce4781cf6008b1c0b416e409fc52065 Signed-off-by: Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63979 Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-30soc/intel/common: Update CSE FW update flow for compressed ME_RW blobsKrishna P Bhat D
In the CSE FW update flow, update is triggered when there is a mismatch in CSE versions. CSE RW blob is directly mapped from SPI flash, hashed, compared and then the CSE RW region is updated. However, in the case of compressed blobs, we cannot directly map the blobs from SPI. It needs to be decompressed before the hash is calculated and compared. Add a check for compressed blobs and figure out whether it needs to be directly mapped from SPI or loaded into memory allocated for file in CBMEM, with the provided CBMEM ID. BRANCH=firmware-brya-14505.B Change-Id: I3bc7708c95272e98702bc25b2334e6e64a93da8a Signed-off-by: Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-30common/block/cse: Add Kconfigs to indicate when CSE FW sync is performedKrishna Prasad Bhat
CSE FW sync is currently performed in romstage, when uncompressed ME_RW blobs are used. When compressed blobs are used, this has to be done in post-RAM stages. Add Kconfigs to describe when the CSE FW sync will be performed, in romstage or in ramstage. BRANCH=firmware-brya-14505.B Change-Id: Iac37aaa5ede5e1cd2d76a58ce2db9cb5b8f42398 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65366 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-28soc/intel: Add Raptor Lake device IDszhixingma
Add Raptor Lake specific CPU, System Agent, PCH, IGD device IDs. References: RaptorLake External Design Specification Volume 1 (640555) 600/700 Series PCH External Design Specification Volume 1 (626817) BUG=b:229134437 BRANCH=firmware-brya-14505.B TEST=Booted to OS on adlrvp + rpl silicon Signed-off-by: Zhixing Ma <zhixing.ma@intel.com> Change-Id: I8e8b9ec6ae82de7d7aa2302097fc66f47b782323 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65117 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-27soc/intel/common/block/gpio: Add gpio pad based functionEric Lai
Introduce three functions: - new_padbased_table: Returns the gpio pad number based table - gpio_padbased_override: Must pass the table with padbased table - gpio_configure_pads_with_padbased: Must pass the table with padbased table, will skip configures the unmapped pins by check pad and DW0 are 0. Some boards may have complex, SKU-based GPIO programming. This patch provides for a simpler pattern of controlling overrides of GPIO programming by providing a table of pad configuration indexed by pad number. Thus, pad state can be overwritten over multiple overrides until the final takes place, and then all GPIO programming is performed at once. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I8b99127b73701b50a7f2e051dee9d12c9da9b741 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64712 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-24soc/intel: Move top_swap Kconfig symbols into soc/intel/commonMartin Roth
Move the Intel top_swap feature into the intel/common Kconfig file. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I3ed649aaeb51c2250be9473114c17d3f191d2c38 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-22soc/intel: Add Meteor Lake SA device IDSubrata Banik
Add Meteor Lake SA device ID 0x7d14 (4+8, 15W). BUG=b:224325352 TEST=Able to build MTL SoC and verified SA DID is now shown proper. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I051a40136ed89e837945bf4569c77d2a80375ed6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65111 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22soc/intel/mp_init: Skip before_post_cpus_init if !USE_COREBOOT_MP_INITSubrata Banik
This patch ensures all APs finish the task and continue before_post_cpus_init() if coreboot decides to perform multiprocessor initialization using native coreboot drivers instead of using FSP MP PPI implementation. BUG=b:233199592 TEST=Build and boot google/kano to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3b76974ab19323201bf1dca9af423481a40f65c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65173 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22soc/intel/cmn/block/cpu: Perform PRMRR sync on all coresSubrata Banik
This patch ensures to perform core PRMRR sync if SoC decides to perform MP Init using coreboot native implementation. Also, implement a function to allow calling `init_core_prmrr()` for all CPUs from `before_post_cpus_init()`. BUG=b:233199592 TEST=Build and boot google/kano to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9b6222c98ff278419fa8411054c0954689e1271e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64978 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22intel/mp_init: Call `intel_reload_microcode()` before post_cpus_init()Subrata Banik
This patch calls into `intel_reload_microcode() function to load second microcode patch after BIOS Done bit is set and before setting the BIOS Reset CPL bit. Also, remove redundant microcode reloading debug print. BUG=b:233199592 TEST=Build and boot google/kano to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Icb3fcfd7ef5478be0a40f8f1358f55c0247b4914 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65157 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22device/resource: Add _kb postfix for resource allocatorsKyösti Mälkki
There is a lot of going back-and-forth with the KiB arguments, start the work to migrate away from this. Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-17soc/intel/{alderlake, common}: Rename the pre_mem_ft structureSridhar Siricilla
The patch renames identifiers (macros, function and structure names) in the basecode/debug/debug_feature.c to generic names so that they can be used to control the features which may have to be controlled either during pre and post memory. Currently, the naming of identifiers indicate that it meant to control the features which can be controlled during only pre-memory phase. TEST=Build code for Gimble Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I53ceb25454027ab8a5c59400402beb6cc42884c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-17soc/intel/denverton_ns: enable Denverton to use common SoC SPI codeJeff Daly
Use Intel common SoC SPI code for Denverton refactor Signed-off-by: Jeff Daly <jeffd@silicom-usa.com> Change-Id: Ic1d57c6b348adb934785b0e2bec4e856f0bf8d77 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61014 Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-15soc/intel/common: support for configurable memory regions claimed by SAEran Mitrani
see https://review.coreboot.org/c/coreboot/+/65072/8 BUG=b:149830546 BRANCH=firmware-brya-14505.B TEST='emerge-brya coreboot chromeos-bootimage' builds correctly. Tested on an Anahera device which successfully boots to ChromeOS with kernel version 5.10.109-15688-g857e654d1705. Change-Id: I80df95f9146934d6a2d23e525c22be3a9a7e2b9f Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64677 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-15soc/intel/common/acpi: Fix warning in ASLVarshit B Pandya
Warnings are treated as errors in build. UBAR is declared inside APRT method which throws warning as follows "Static OperationRegion should be declared outside control method" Move UBAR outside APRT method to fix warning. TEST=build brya with following changes without any warnings 1. Select ACPI_CONSOLE 2. Include <soc/intel/common/acpi/acpi_debug.asl> 3. Add APRT function in any asl file. Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I40c676fd0bbd529bcbded18dd248b918f47324d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2022-06-14soc/intel/cmn/cpu: API to initialize core PRMRRSubrata Banik
This patch implements API to sync between core PRMRR(Processor Reserved Memory Range Registers). Read PRMRR base and limit value from BSP and apply it on the rest of the cores. BUG=b:233199592 TEST=Build and boot google/taeko to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I720669139429afc3d8c8d15c0ce15f1524f22e4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-06-14soc/intel/common: Remove use of CPUID_EXTENDED_CPU_TOPOLOGY_V2Ronak Kanabar
In x86 processor as per Software Developer's manual there are 2 ways to get CPU topology by querying the processor. BIOS can use CPUID instruction using CPUID_EXTENDED_CPU_TOPOLOGY (0x0B) as input or CPUID_EXTENDED_CPU_TOPOLOGY_V2 (0x1F) as an input. Both will return valid CPU topology data. While CPUID_EXTENDED_CPU_TOPOLOGY (0x0B) returns data related to number of threads, core and package, CPUID_EXTENDED_CPU_TOPOLOGY_V2 (0x1F) provides more granular information regarding Die, package etc. coreboot uses V2 to in order to query and return CPU topology data as of now since that's the highest instruction of CPUID which is supported, there is a mismatch in the way FSP processes the data. FSP queries coreboot MP services to get CPU topology data which uses structure which is either compatible with CPUID_EXTENDED_CPU_TOPOLOGY or CPUID_EXTENDED_CPU_TOPOLOGY_V2. Since coreboot returns V2 data in structure which is expecting data for CPUID_EXTENDED_CPU_TOPOLOGY, there is hang observed on ADL_N CPUs. To solve this problem coreboot should assign CPUID_EXTENDED_CPU_TOPOLOGY data to processor_info_buffer->Location structure so remove use of CPUID_EXTENDED_CPU_TOPOLOGY_V2 Ref EDK2 code: https://github.com/tianocore/edk2/tree/edk2-stable202202 Files: MdePkg/Include/Protocol/MpService.h#L182 UefiCpuPkg/Library/MpInitLib/MpLib.c#L2127 UefiCpuPkg/Library/MpInitLib/MpLib.c#L2120 Ref doc: Software Developer’s Manual volume 3 CH 8.9 BUG=b:220652104 TEST=Build and boot ADL-N RVP with debug FSP and verify CPU topology value and observe system boots (no hang). Change-Id: I1e6832fb03fcc59d33df0ba1664019727185d10a Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-06-12soc/intel/lpc: Set up default LPC decode rangesArthur Heymans
Intel LPC devices have generic and fix IO decode ranges. This CL is smarter about using generic ones, by using the fixed ones first. Change-Id: Ifd98bcc639ee08d068956a33b0e12cc70211ca2d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65097 Reviewed-by: Marvin Drees <marvin.drees@9elements.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-09soc/intel/cmn/mp_init: Reload microcode patch before post_cpus_init()Subrata Banik
This patch provides an option for CPU programming where coreboot expected to load second microcode patch after BIOS Done bit is set and before setting the BIOS Reset CPL bit. BUG=b:233199592 TEST=Build and boot google/taeko to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I426b38cb1200e60398bc89515838e49ce0a98f06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64836 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-09soc/intel/alderlake: Add support for PCIe slot & device detect timeoutCliff Huang
1. add timeout for root port detection and pass to FSP. 2. add 'slot implemented' flag and pass to FSP. 3. PcieRpSlotImplemented needs to be set when the root port is set to hotplug. There is an assertion in FSP checking this. 4. PcieRpSlotImplemented is updated only when it is built-in as it is default to slot implemented in FSP. BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I13feb1d2d67eaba634a3e700685132fba39e1525 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-07soc/intel/cmn/mp_init: Create helper function to load microcodeSubrata Banik
This patch creates a helper function named `initialize_microcode()` to load microcode and ease for all function to peform loading microcode using this helper function. BUG=b:233199592 TEST=Build and boot google/taeko to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7155fc2da7383629930ce147a90ac582782fa5ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/64835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-06-07soc/intel/cmn/block/cpu: Set BIOS_DONE on all CPUsSubrata Banik
As per Intel Processor EDS, BIOS_DONE bit needs to be set on all CPUs via MSR. Also, implement a function to perform any SoC recommended CPU programming prior to post CPUs init. At present calling `cpu_soc_bios_done()` for all CPUs from `before_post_cpus_init()`. Note: It is expected that `before_post_cpus_init()` will be extended with other CPU programming recommendations in follow up patches, for example: reload microcode patch etc. BUG=b:233199592 TEST=Build and boot google/taeko to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8066cd724c9f15d259aeb23f3aa71a2d224d5340 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-06-07soc/intel/cmn/cse: Implement heci_init() to initialize HECI devicesSubrata Banik
This patch implements heci_init() API that perform initialization of all HECI devices as per MAX_HECI_DEVICES config. BUG=none TEST=Able to build and boot google/taeko with this change. No CSE error observed with `heci_init()` called from romstage. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia25e18a20cc749fc7eee39b0b591d41540fc14c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-04soc/intel/cmn/cse: Fix return type for `devfn`Subrata Banik
This patch fixes the return type for `devfn` variable inside heci_set_to_d0i3(). `PCI_DEVFN` macro returns `unsigned int` instead of `pci_devfn_t`. TEST=Able to build and boot to ChromeOS without any failure. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib3a575aa7d71cbe6932e823917b57c5558387433 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-04soc/intel: Rename heci_init to cse_initSubrata Banik
This patch renames heci_init() to cse_init() as HECI initialization should have a bigger scope than just initializing the CSE (a.k.a HECI1 alone). BUG=none TEST=Able to build and boot google/taeko. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic7edd55ccdcd70b244615fa06f81803a0ae6ce80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-03drivers/wifi: Move MTL Magnetar CNVi DIDs from SoC to generic driverSubrata Banik
This patch removes the MTL CNVi DIDs macros from IA common code and is added into the generic wifi driver. As per Intel Connectivity Platform BIOS Guide, Connectivity Controller IP for MTL-P is `Magnetar` and supported CRF is `Typhoon Peak 2`. Previously Garfield Peak DIDs for Alder Lake SoC also added similarly to generic wifi drivers. BUG=b:224325352 TEST=Able to build and boot on MTL emulator. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib98762749c71f63df3e8d03be910539469359c68 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2022-06-03intelblocks/gpio.c: Handle NULL return values from child functionsMaulik V Vaghela
gpio_configure_pad function gets called for most of the GPIO configuration for all the boards. This function is not handling NULL pointers properly which can cause exception in CPU. This patch fixes the handling and function is able to return early in case the NULL pointer is passed or any subsequent child function calls return NULL. BUG=None BRANCH=None TEST=Compilation works fine for all Alder Lake boards. Change-Id: I97fad72cdd92f70c7c5e6fdd23fbecf535a6e388 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-03intel/common/block: move RAPL disabling to common codeUwe Poeche
This patch brings the feature of disabling RAPL to common code. It replaces the current solution for APL and EHL. For special case if RAPL disabling is only working via changes in MCHBAR a new config switch was introduced. Test: Boot mc_apl4/5 with this patch and ensure that the relevant bits in MSR 0x610 are the same as before the patch. Change-Id: I2098ddcd2f19e3ebd87ef00c544e1427674f5e84 Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-06-02soc/intel/common/cpu: Use SoC overrides to set CPU privilege levelSubrata Banik
This patch implements a SoC overrides to set CPU privilege level as the MSR is not consistent across platforms. For example: On APL/GLK/DNV, it's MSR 0x120 and CNL onwards it's MSR 0x151. BUG=b:233199592 TEST=Build and boot google/taeko to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4584516102560e6bb2a4ae8c0d036be40ed96990 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-06-01soc/intel/fast_spi: Use smarter mtrr code in ramstageArthur Heymans
mtrr_use_temp_range is a lot smarter than the plain set_var_mtrr. It will compute a new optimal solution with the temp ranges included while also taking care of the cleanup before loading the payload/s3 resume. Change-Id: I283ba07fc12c410be39dfdc828657598237247c1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63550 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-28soc/intel/common: Use coreboot error codesSridhar Siricilla
The patch uses coreboot error codes instead of uint8_t data type in the pre_mem_debug_init function. TEST=build code for Gimble Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I957ff764900cb789bf2aacf0472dcb281f48af07 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2022-05-26soc/intel/skylake: Move FSP_HYPERTHREADING to common Intel KconfigFelix Singer
Move the Kconfig option `FSP_HYPERTHREADING` to common Intel Kconfig so that it can be reused by other SoCs. Since not all SoCs support hyperthreading, make it conditional on `HAVE_HYPERTHREADING`. SoCs supporting hyperthreading need to select it so that `FSP_HYPERTHREADING` is available. Change-Id: I892d48b488cbf828057f0e9be9edc4352c58bbe7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-05-25soc/intel/common: Skip sending DISCONNECT IPC commandSridhar Siricilla
The patch skips sending DISCONNECT IPC command to PMC if system resumes from S3. coreboot notice DISCONNECT IPC command getting timedout during S3 resume if system has AC connected behind Type-C hub. This impacts system resume time. Please refer TA# 730910 for more information. coreboot need not send the DISCONNECT IPC command when system resumes from S3 state. TEST=Verified system boots to OS and verfied below tests on Gimble 1. coreboot doesn't send the DISCONNECT during S3 resume 2. After S3 resume, system detects the pen drive with Superspeed 3. After system resumes from S3, hot-plug the pen drive, system detects the pen drive 3. System sends IPC commands when system boots from S0 or S5. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I6ad006ae8677919c7dfeca8eec0af11454a2e89d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-05-25arch/x86/acpi_bert_storage.c: Use a common implementationArthur Heymans
All targets now use cbmem for the BERT region, so the implementation can be common. This also drops the obsolete comment about the need to have bert in a reserved region (cbmem gets fixed to be in a reserved region). Change-Id: I6f33d9e05a02492a1c91fb7af94aadaa9acd2931 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-05-24soc/intel/cmn/fast-spi: Add BIOS MMIO window as reserved regionWerner Zeh
Add the boot flash MMIO window to the resources to report this region as reserved to the OS. This is done to stay consistent with the reserved memory ranges by coreboot and make the OS aware of them. As x86 systems preserves the upper 16 MiB below 4G for BIOS flash decoding use the complete window for reporting independent of the actually used SPI flash size. This will block the preserved MMIO window. Change-Id: Ib3a77e9233c3c63bad4de926670edb4545ceaddf Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-05-21src/soc/intel/cmn/fast-spi: Add SSDT extension to fast SPI driverWerner Zeh
If the SPI controller is hidden from the OS (which is default on Apollo Lake) then OS has no chance to probe the device and therefore can not be aware of the resources this PCI device occupies. If the OS needs to move some resources for a reason it can happen that the new allocated window will be shadowed by the hidden PCI device resource and hence causing a conflict. As a result this MMIO window will be inaccessible from the OS which will cause issues in applications. For instance on Apollo Lake this causes flashrom to stop working. This patch adds a SSDT extension for the PCI device if it is hidden from the OS and reports the occupied resource via ACPI to the OS. For the cases where the device is hidden later at coreboot runtime and therefore is not marked as hidden in the PCI device itself a Kconfig switch called 'FAST_SPI_GENERATE_SSDT' is introduced. It defaults to 'no' and can be set from SOC code to override it. Since there is no defined ACPI ID for the fast SPI controller available now, the generic one (PNP0C02) is used. Test: Boot mc_apl4 and make sure flashrom works again. Change-Id: Ia16dfe6e001188aad26418afe0f04c53ecfd56f1 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-05-20CBMEM: Change declarations for initialization hooksKyösti Mälkki
There are efforts to have bootflows that do not follow a traditional bootblock-romstage-postcar-ramstage model. As part of that CBMEM initialisation hooks will need to move from romstage to bootblock. The interface towards platforms and drivers will change to use one of CBMEM_CREATION_HOOK() or CBMEM_READY_HOOK(). Former will only be called in the first stage with CBMEM available. Change-Id: Ie24bf4e818ca69f539196c3a814f3c52d4103d7e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-19soc/intel/common/block/smbus: Deduplicate some codeAngel Pons
Reuse existing SMBus code from southbridge/intel/common/smbus_ops.h. Change-Id: Iea4f6886bb49590f7f96abbfbe631ac9d4dda902 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64432 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-18intel/common/block: Provide RAPL and min clock ratio switches in commonUwe Poeche
There are two APL specific config switches for RAPL and min. cpu clock (APL_SKIP_SET_POWER_LIMITS, APL_SET_MIN_CLOCK_RATIO). These switches could be used in future in other CPU platforms. Move them to common code instead of having them just for one SOC. Test: Make sure that the clock ratio (MSR 0x198) and the RAPL settings (MSR0x610) do not change with this patch applied on mc_apl{1,4,5} mainboard. Change-Id: I3d63d1b9b6c96586a3c20bf8c1d8001b1d7c4bed Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-16soc/intel: Add Raptor Lake device IDsBora Guvendik
Add Raptor Lake specific CPU, System Agent, PCH, IGD device IDs. References: RaptorLake External Design Specification Volume 1 (640555) 600/700 Series PCH External Design Specification Volume 1 (626817) Change-Id: I39e655dec2314a672ea63ba90d8bb3fc53bf77ba Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
2022-05-16soc/intel/common: Implement IOC driverWonkyu Kim
Starting with Meteor Lake SoC, the PCR/DMI interface to program GPMR is replaced with IOC (I/O Cache), hence, this patch implements IOC driver to support that migration. Reference: 643504 MTL FAS section 7.5.2 TEST=Build and boot to OS for TGL RVP and MTL PSS Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I768027c2ca78310c03845f70f17df19dc8cd0982 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63198 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-16soc/intel/cmn/spi: Separate fast SPI device from generic SPI driverWerner Zeh
The fast SPI controller (usually handling the boot NOR flash) is a different controller type than the generic SPI controllers as it provides access to the boot flash and usually is not used for generic SPI slave connections. Though there is common code for the fast SPI controller it currently do not uses the PCI driver structure. This patch adds the PCI driver envelope to the fast SPI driver and moves Apollo Lake as the first platform to this driver. Change-Id: I31bf39ec1c622db887dec9ca8623a7f282402849 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-16soc/intel/*: Use SSDT to pass A4GB and A4GSArthur Heymans
GNVS is more fragile as you need to keep struct elements in sync with ASL code. Change-Id: I2cd5e6b56e4a0dbbb11f4a0ac97e8f84d53b90ec Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-05-16soc/intel/common: Consistently use smbus 7-bit address log formatKane Chen
The "No memory dimm at address" line in get_spd_sn and get_spd fucntion have different format of SPD address. get_spd_sn shows a 8-bit address format but get_spd shows a 7-bit address format when there is no DIMM connected. It can be confusing when debugging. Change-Id: I46a006f4024b12d27ae0a933b7c40515034d5d64 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Chen <jamie.chen@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16intelblocks/gpio: Optimize GPIO functions by passing group and pin infoMaulik V Vaghela
There were 3 different functions in gpio.c file which used to get gpio group and pin information separately through function calls. Since these are static function, we can modify argument to pass group and pin information from parent/calling function. This will reduce redundant work of getting information 3 times separately. BUG=None BRANCH=None TEST=code compiles and correct information is passed to functions. Check by using pin information on Brya. Change-Id: Ie92be8c22838ebc5e831be58545e2023eecfff24 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16intelblocks: Add function to program GPE_EN before GPIO lockingMaulik V Vaghela
Since coreboot locks GPIO registers after GPIO configuration, OS is not able to program GPE_EN register to program wake events. This causes the issue of event not getting logged into event log (since GPE_EN bit is not set). GPE_EN register programming is required for the GPIO pins which are capable of generating SCI for the system wake. Elog mechanism relies on GPE_EN and GPE_STS bit to log correct wake signal. This patch add supports to program GPE_EN register before coreboot locks the GPIO registers. Note that coreboot will only program GPE_EN bits for GPIO capable of generating SCI. This will help resolve issue where we don't see wake event GPIO in event log. BUG=b:222375516 BRANCH=firmware-brya-14505.B TEST=Compile code for Brya and see GPE_EN bits set from the kernel console Change-Id: I27e525f50c374c2cc9675e77eaa7774683a6e7c2 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16soc/inte/*/gpio; Add GPE_EN and GPE_STS register definitionMaulik V Vaghela
coreboot needs to set GPE_EN bit for the GPIOs which are wake capable from s0ix/sleep. Due to GPIO locking mechanism, coreboot/OS will not be able to write GPE_EN register post GPIO has been locked. This patch adds support in SoC code to provide correct offset for GPE_EN and GPE_STS registers to the common code. Plan is to use this offsets to set GPE_EN bits before GPIO locking in coreboot which will be part of subsequent CL. BUG=b:222375516 BRANCH=firmware-brya-14505.B TEST=Check if code compiles for Brya and correct offset values are printed. Change-Id: I6b813b30b8b360f8eccbf539b57387310e380560 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16soc/intel/common: Use mp_run_on_all_cpus_synchronously for APs MTRR initKane Chen
By using mp_run_on_all_cpus_synchronously to run APs MTRR init, it gurantees the BSP will run post_cpus_add_romcache until all APs finishes _x86_setup_mtrrs task. BUG=b:225766934 TEST=Test on redrix and found the MTRR race condition on AP/BSP is gone. Change-Id: I1fd889f880a0c605e6c739423a434d2adbc12d26 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-05-16soc/intel/common/block/smbus: Add smbus block read write functionsShelly Chang
Signed-off-by: Shelly Chang <Shelly_Chang@wiwynn.com> Change-Id: Ib795f25abe5bbd95555b68af39c637d7c93aa819 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64251 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-16src: Remove unused <cf9_reset.h>Elyes Haouas
Found using: diff <(git grep -l '#include <cf9_reset.h>' -- src/) <(git grep -l 'RST_CNT\|FULL_RST\|RST_CPU\|SYS_RST\|do_system_reset\|do_full_reset\|cf9_reset_prepare\|system_reset\|full_reset' -- src/) |grep "<" Change-Id: I093d8412e14ce81b462fb9a7ccb3a2a93ae760a6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16soc/intel: Remove unused <cpu/intel/common/common.h>Elyes HAOUAS
Change-Id: I25d112941db8214a7e450de5fb512ef8c2c5f5e2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-14soc/intel/acpi_bert.c: Fix formatted print type for size_tArthur Heymans
Change-Id: I2b02bcecda2257f191c0d0fc9935b1eb673ab3d2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64335 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-05-13soc/intel/block/crashlog: Remove unused variableArthur Heymans
Change-Id: I2f89d11c163f56163d5c361a3edad14418bf9fa7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-12soc/intel/alderlake: provide a list of D-states to enter LPMTarun Tuli
Implement sub-function 1 (Get Device Constraints) of the Low Power S0 Idle Device-Specific Method (_DSM). This provides a way in which to describe various devices required D-states to enter LPM (S0ix). The information can be used to help in diagnostics and understanding of S0ix entry failure. Values were derived from Intel document 595644 (rev 0.45) and the ADL FSP sample ASL. This implementation adds support for ADL. Other SoC's could be ported to be included as well. If they aren't, they will default to the existing behavior of a single hardcoded device to ensure compatibility with Windows. TEST=Built and tested on brya by verifying SSDT contents Change-Id: Ibe46a0583c522a8adf0a015cd3a698f694482437 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lance Zhao
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