diff options
| author | Wonkyu Kim <wonkyu.kim@intel.com> | 2022-08-03 12:47:06 -0700 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-08-12 07:29:14 +0000 |
| commit | 91bd6e19c92ed7984b4a0c7985c58512879e7a56 (patch) | |
| tree | fc9428ff8bab252b60c38d07886c7ebdef9d5ef1 /src/soc/intel/common | |
| parent | 9969f4b60928f6e1de7941f09afb70a2f27aa7ef (diff) | |
soc/intel/common: Ignore prefetch PCI attribute for IGD BAR0
From Meteorlake, IGD BAR0(GTTMMADR) is changed to 64bit prefetchable.
Due to the prefetchable attribute, resource allocation for IGD BAR0 is
assigned WC memory and it causes kernel driver failure.
For avoiding kernel driver failure, ignore prefetch PCI attribute
for IGD BAR0 to assign UC memory.
We're working on publishing below information.
- IGD BAR0(GTTMMADR) is changed to 64bit prefetchable BAR
- GTTMMADDR BAR should be always mapped as UC memory although
marked Pre-fetchable.
BUG=b:241746156
TEST=boot to OS and check guc driver loading successful
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I76d816d51f32f99c5ebcca54f13ec6d4ba77bba5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66403
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/block/graphics/Kconfig | 7 | ||||
| -rw-r--r-- | src/soc/intel/common/block/graphics/graphics.c | 13 |
2 files changed, 19 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/graphics/Kconfig b/src/soc/intel/common/block/graphics/Kconfig index bc07f5626f..8520e53562 100644 --- a/src/soc/intel/common/block/graphics/Kconfig +++ b/src/soc/intel/common/block/graphics/Kconfig @@ -29,4 +29,11 @@ config SOC_INTEL_GFX_FRAMEBUFFER_OFFSET with GTT_SIZE value. On SoC platform where PCI config offset 0x18 points to the GMADR directly can use the default value 0x0 without any override. +config SOC_INTEL_GFX_NON_PREFETCHABLE_MMIO + bool + default n + help + Ignore BAR0(offset 0x10)'s pre-fetchable attribute to use non-prefetchable + MMIO to fix OS display driver failure. + endif diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index d13b322e90..e4ef458631 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -164,8 +164,19 @@ void graphics_gtt_rmw(unsigned long reg, uint32_t andmask, uint32_t ormask) graphics_gtt_write(reg, val); } +static void graphics_dev_read_resources(struct device *dev) +{ + pci_dev_read_resources(dev); + + if (CONFIG(SOC_INTEL_GFX_NON_PREFETCHABLE_MMIO)) { + struct resource *res_bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res_bar0->flags & IORESOURCE_PREFETCH) + res_bar0->flags &= ~IORESOURCE_PREFETCH; + } +} + static const struct device_operations graphics_ops = { - .read_resources = pci_dev_read_resources, + .read_resources = graphics_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gma_init, |