diff options
| -rw-r--r-- | src/soc/intel/common/block/graphics/Kconfig | 7 | ||||
| -rw-r--r-- | src/soc/intel/common/block/graphics/graphics.c | 13 |
2 files changed, 19 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/graphics/Kconfig b/src/soc/intel/common/block/graphics/Kconfig index bc07f5626f..8520e53562 100644 --- a/src/soc/intel/common/block/graphics/Kconfig +++ b/src/soc/intel/common/block/graphics/Kconfig @@ -29,4 +29,11 @@ config SOC_INTEL_GFX_FRAMEBUFFER_OFFSET with GTT_SIZE value. On SoC platform where PCI config offset 0x18 points to the GMADR directly can use the default value 0x0 without any override. +config SOC_INTEL_GFX_NON_PREFETCHABLE_MMIO + bool + default n + help + Ignore BAR0(offset 0x10)'s pre-fetchable attribute to use non-prefetchable + MMIO to fix OS display driver failure. + endif diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index d13b322e90..e4ef458631 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -164,8 +164,19 @@ void graphics_gtt_rmw(unsigned long reg, uint32_t andmask, uint32_t ormask) graphics_gtt_write(reg, val); } +static void graphics_dev_read_resources(struct device *dev) +{ + pci_dev_read_resources(dev); + + if (CONFIG(SOC_INTEL_GFX_NON_PREFETCHABLE_MMIO)) { + struct resource *res_bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res_bar0->flags & IORESOURCE_PREFETCH) + res_bar0->flags &= ~IORESOURCE_PREFETCH; + } +} + static const struct device_operations graphics_ops = { - .read_resources = pci_dev_read_resources, + .read_resources = graphics_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gma_init, |