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2023-02-01treewide: Remove duplicated include <device/pci.h>Elyes Haouas
<device/pci.h> chain-includes <device/pci_def.h> & <device/pci_type.h>. Change-Id: I4e5999443e81ee1c4b1fd69942050b47f21f42f8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72626 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-31soc/intel/common/block: Add LPC BIOS decode lockTim Chu
The LPC BIOS decode lock bit is defined in EBG EDS documentation. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I60df7e6da2b22b8eeb2094aeb5ee9667043bb30b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71954 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-28soc/intel/common/block/acpi/pep: use acpigen_write_processor_namestringFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I43590f0f792fca1c90ee8f8b32e6be47943c59df Reviewed-on: https://review.coreboot.org/c/coreboot/+/72453 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-27intelblocks/cse: Add functions to check and change PTT stateMichał Żygowski
Add functions that allow checking and changing PTT state at runtime. Can be useful for platforms that want to use dTPM instead and have no means to stitch ME firmware binary with disabled PTT. The changing function also checks for the current feature states via HECI to ensure that the feature state will not be changed if not needed. TEST=Successfully switch to dTPM on Comet Lake i5-10210U SoC. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I8426c46eada2d503d6ee72324c5d0025da3f2028 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2023-01-26soc/intel/alderlake: Wait for panel power cycle to completeJeremy Compostella
The Alder Lake PEIM graphics driver executed as part of the FSP does not wait for the panel power cycle to complete before it initializes communication with the display. It can result in AUX channel communication time out and PEIM graphics driver failing to bring up graphics. If we have performed some graphics operation in romstage, it is possible that a panel power cycle is still in progress. To prevent any issue with the PEIM graphics driver it is preferable to ensure that panel power cycle is complete. This patch replaces commit ba2cef5b5493 ("soc/intel/common/block/early_graphics: Introduce a 200 ms delay") workaround patch. BUG=b:264526798 BRANCH=firmware-brya-14505.B TEST=Developer screen is visible in the recovery flow Change-Id: Iadd6c9552b184f7d6ec8df9d0d392634864ba50b Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72419 Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-01-26drivers/intel/gma: Use libgfxinit Update_Output to turn off graphicsJeremy Compostella
We were using the libgfxinit `Initialize' function with the `Clean_State' parameter because the more appropriate `Update_Output' function was not performing all the necessary clean up operations for the PEIM driver to be successful when libgfxinit was used in romstage. Thanks to a lot of experiments and some log analysis efforts, we were able to identify the missing operation and fix the `Update_Output' function (cf. https://review.coreboot.org/c/libgfxinit/+/72123). The `initialized' global variable is now unnecessary as we track the initialization in the Ada code instead. Since the `Update_Output' function does not return any value, this patch modifies the `gma_gfxstop' prototype accordingly. This does not have any impact as the return value was not used anyway. BUG=b:264526798 BRANCH=firmware-brya-14505.B TEST=Developer screen is visible Change-Id: I53d6fadf65dc09bd984de96edb4c1f15b64aeed0 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72125 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-01-25soc/intel/common/gpio: Add function to read GPIO TX valueCliff Huang
This function reads out the current value set to output for a GPIO pin. Ex: GPP_E0 is set to output int e0_val; e0_val = gpio_tx_get(GPP_E0); Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Ib02b9ab50d378eb163d91aed1576428b49cec2cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/72127 Reviewed-by: Anil Kumar K <anil.kumar.k@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2023-01-25soc/intel/cmn/block/pcie: Make ASPM configurableMaximilian Brune
Currently ASPM cannot be disabled by individual mainboards, if the soc Kconfig includes SOC_INTEL_COMMON_PCH_CLIENT. Other options like PCIEXP_CLK_PM and PCIEXP_L1_SUB_STATE are already configurable by individual mainboards if needed. This change makes PCIEXP_ASPM one of these configurable options. Test: build prodrive/atlas and see that build/config.h lists the option CONFIG_PCIEXP_ASPM as disabled. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Ic9c049f1d225bc21d8da5bd208651ad847ae0c6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/72117 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-24soc/intel/cmn/block: Add smbus/p2sb device ids for SPR-SPTim Chu
Intel SPR-SP (Sapphire Rapids Scalable Processor) was product launched on Jan. 10, 2023. The chipset includes Emmitsburg PCH. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I05ed8f753bf63b6cb3035e973eb6a7974edfd673 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-01-24soc/intel/cmn/pmc: Clear GEN_PMCON_x register power failure status bitsSubrata Banik
This patch calls into `pmc_clear_pmcon_pwr_failure_sts()` to clear GEN_PMCON_x register status bits after determining the `prev_sleep_state`. Having those bits being set across reboot might be misleading. For example: although the last boot was not due to power failure but the power failure bit still remains the same (unless cleared). Note: clearing `GBL_RST_STS` bit earlier than FSP-M/MRC having an adverse effect on the PMC sleep type register which results in calculating wrong `prev_sleep_state` post a global reset, hence, just clearing the power failure status bits rather than clearing the complete PMC PMCON_A register. BUG=b:265939425 TEST=Able to clear the GEN_PMCON_A register power failure bits aka BIT16 and BIT14 on google/marasov platform over next boot to avoid having its persistent effect. Without this patch: pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00 ... GEN_PMCON: d0215238 00002200 With this patch: pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00 ... GEN_PMCON: d1001038 00002200 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4f5dfe0251aeb85b667fbfc44fbf17b025aec090 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-01-24soc/intel/cmn/pmc: Create API to clear PMC power failure status bitsSubrata Banik
This patch implements an API named `pmc_clear_pmcon_pwr_failure_sts()` to clear power failure status bits of PMC General PM Configuration A/B based on the underlying SoC. Based on the available PMC register definitions between Sky Lake till latest Meteor Lake platform, the SoC platform that selects SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION config has power failure bits mapped into the MMIO mapped GEN_PMCON_A register where else for the other SoCs, those power failure bits are belongs to the PCI config space mapped GEN_PMCON_B register. BUG=b:265939425 TEST=Able to build the google/marasov. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Icbbe47ccfd489edf9c38f52bdf7cf2de7aa9eedf Reviewed-on: https://review.coreboot.org/c/coreboot/+/72053 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-01-24soc/intel/common/cse_lite: Allow specific operation prior to updateJeremy Compostella
Some boards may want to perform a specific operation before the CSE FW update final operation begins. For instance, on Brya this new callback can be used to inform the end-user that an update is in progress. BUG=b:264648959 BRANCH=firmware-brya-14505.B TEST=Compilation success Change-Id: Ia4d32a71f3ae61d2e24197fee6b458512f7778a9 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72097 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-22intel/common/block: Fix potential buffer overflowBora Guvendik
Possible Buffer Overflow - Array Index Out of Bounds. Array regions size is 256 but 'i' iterates from 0 to 256. Found-by: Klockwork BUG=None BRANCH=firmware-brya-14505.B TEST=Boot to OS Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Iee45a5821b9dd3f9e6f9816599beebf34555426d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72049 Reviewed-by: Hannah Williams <hannah.williams@intel.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20soc/intel: Remove unused <stddef.h>Elyes Haouas
Change-Id: I8432d799c9bf23058b7b903bb07f6c2b4308eeba Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72103 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20soc/intel/common/block/fast_spi/Makefile.inc: Remove spaces before tabsElyes Haouas
Change-Id: Id2b408e24f74367777b1b949623d6692f2f19e6d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72076 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-01-19tree: Drop Intel Ice Lake supportFelix Singer
Intel Ice Lake is unmaintained and the only user of this platform ever was the Intel CRB (Customer Reference Board). As it looks like, it was never ready for production as only engineering sample CPUIDs are supported. As announced in the 4.19 release notes, remove support for Intel Icelake code and move any maintenance on the 4.19 branch. This affects the following components and their related code: * Intel Ice Lake SoC * Intel Ice Lake CRB mainboard * Documentation Change-Id: Ia796d4dc217bbcc3bbd9522809ccff5a46938094 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72008 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-16commonlib/storage: Add common eMMC functionsShelley Chen
Now that multiple platforms are trying to initialize eMMC in coreboot instead of depthcharge, lets move common functionality into commonlib instead of copying the same functionality between multiple platforms. Note for consistency, changed name of set_early_mmc_wake_status() to mmc_set_early_wake_status(). Also adding an mmc_send_cmd1() function for retrieving the Operating Conditions Register (OCR) contents. BUG=b:218406702 BRANCH=None TEST=emerge-herobrine coreboot chromeos-bootimage flash onto villager device and make sure still boots ChromeOS Change-Id: Id00535b05bbd379081712601ef10e762c1831747 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-15soc/intel/common: Use 'enum cb_error' valuesSridhar Siricilla
The patch uses 'enum cb_error' values as return values for below functions: 1. cse_get_rw_rdev() 2. cse_erase_rw_region() 3. cse_write_rw_region() 4. cse_locate_area_as_rdev_rw() 5. cse_get_target_rdev() 6. cse_copy_rw TEST=Build, boot and perform CSE downgrade test on the Gimble board Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I9c664430a5015d37b9c329f85886f8622deaa497 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-15soc/intel/common: Use 'enum cb_err' valuesSridhar Siricilla
The patch uses cb_err enum values as return values for function cse_get_boot_performance_data() instead of true/false. TEST=Build code for Gimble Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I0153d5496c96fb0c2a576eef1fe2fa7fa0db8415 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-15soc/intel/common: Use enum cb_err valuesSridhar Siricilla
The patch uses cb_err enum values as return values for below functions: 1. cse_hmrfpo_enable() 2. cse_boot_to_ro() 3. cse_prep_for_rw_update() 4. cse_sub_part_get_target_rdev() 5. cse_get_sub_part_fw_version() 6. cse_prep_for_component_update() Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I1bdb7d6b2051a69f1021673d464bfad63dd39431 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-13soc/intel : Use 'enum cb_err' valuesSridhar Siricilla
Use 'enum cb_err' values for below cse lite functions instead of true or false. Functions whose return values updated in this patch: 1. cse_set_next_boot_partition() 2. cse_data_clear_request() 3. cse_set_and_boot_from_next_bp() 4. cse_boot_to_rw() 5. cse_fix_data_failure_err() TEST= Do boot test on Gimble. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I7fec530aeb617bab87304aae85ed248e51a6966b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-13soc/intel: Use 'enum cb_err' instead of boolSridhar Siricilla
The patch uses 'enum cb_err' values as return values for cse_get_bp_info() function. TEST=Build the code for Gimble Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I900e40b699de344f497e61d974bca3fee7f6ecbf Reviewed-on: https://review.coreboot.org/c/coreboot/+/71821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-12soc/intel/common: Use enum csme_failure_reasonSridhar Siricilla
The patch updates return type for below functions as they uses 'enum csme_failure_reason' type return values. 1. cse_sub_part_trigger_update() 2. handle_cse_sub_part_fw_update_rv() 3. cse_sub_part_fw_update() TEST=Build coreboot code for Gimble Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I43bc2d518a275894860e4d3c930c3c4d9685fb3a Reviewed-on: https://review.coreboot.org/c/coreboot/+/71792 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12soc/intel/common/block/early_graphics: Introduce a 200 ms delayJeremy Compostella
It has been reported that the PEIM graphics driver may temporarily fail communication with the display if the time between libgfxinit turning off the displays and the PEIM driver initialization is too short. 200 ms has been identified as a safe delay. This is a temporary workaround and an investigation is in progress to come up with a better and long term solution. BUG=b:264526798 BRANCH=firmware-brya-14505.B TEST=Developer screen is systematically seen Change-Id: I4ea15123eed1a4355c5ff7d815925032d4151de1 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71656 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12soc/intel/common/block: Add Intel VGA early graphics supportJeremy Compostella
This patch introduces an early graphics driver which can be used in romstage in cache-as-ram mode. The implementation relies on `libgfxinit' and provide VGA text mode support. SoCs wanting to take advantage of this driver must implement the `early_graphics_soc_panel_init' function to set the panel power sequence timing parameters. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=Graphics bring up observed on skolas with extra patches Change-Id: Ie4ad1215e5fadd0adc1271b6bd6ddb0ea258cb5b Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70299 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Maulik Vaghela <maulikvaghela@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11drivers/intel/gma: Hook up libgfxinit in romstageJeremy Compostella
A mainboard port needs to: - select `CONFIG_MAINBOARD_HAS_EARLY_LIBGFXINIT' - implement the Ada package `GMA.Mainboard' with a single function `ports' that returns a list of ports to be probed for displays. - set the desired `GFX_GMA_DEFAULT_MMIO' IO memory address to use in romstage (and ramstage) for the graphic device. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=libgfxinit compiles in romstage. libgfxinit successfully executes in romstage and ramstage using the requested MMIO setting on skolas. Change-Id: I3c2101de10dc5df54fe873e43bbe0f1c4dccff44 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70276 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-10soc/intel: Add Kconfigs to define scaling factor for coresSridhar Siricilla
The patch adds Kconfigs to define scaling factor for Efficient and Performance cores instead of using hard coded values in the soc code. Also, the patches uses the Kconfigs directly to calculate the core's nominal performance. So, we don't need to implement soc function soc_get_scaling_factor() to get the scaling factor data for different core types. Hence, soc_get_scaling_factor() function is removed. TEST=Build the code for Gimble and Rex. Also, I have verified that build system logs error when the Kconfigs are undefined. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I55e4d815116ef40c5f33be64ab495e942bf35ee8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71687 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-09soc/intel/common: Fix cpu index calculationSridhar Siricilla
get_cpu_index() helper function returns cpu's index based on it's APIC id position from the ascending order list of cpus' APIC IDs. In order to calculate the cpu's index, the helper function needs to traverse through each cpu node to find their APIC IDs. So, the function traverse the CPU node list from the cpu whose APIC ID is 0 assuming it is the first cpu node in the list. This logic works fine where BSP's APIC ID is 0. But, starting from MTL, APIC ID for BSP need not be 0 as APIC ID numbering first get assigned for CPU Die Efficient cores, then Performance cores. Please refer section# 6.1 of doc#643504 for more details on APIC IDs. Considering the APIC Id allotment for MTL cores, as existing code traversing begins from the cpu that has APIC Id#0 which may not be the first cpu node in the list so index calculation results in wrong value. The patch addresses above described issue by traversing all the CPU nodes to calculate the cpu index. Also, prevents inconsistent report of /sys/devices/system/cpu/cpu*/cpufreq/* and /sys/devices/system/cpu/cpuXX/acpi_cppc on each reboot. TEST=Verified that the get_cpu_index helper function returns the correct index id for a CPU on Rex. The coreboot log with code instrumentation, before this patch: [DEBUG] my_apic_id:0x10 cpu_index: 0x6 [DEBUG] my_apic_id:0x11 cpu_index: 0x6 [DEBUG] my_apic_id:0x42 cpu_index: 0x6 [DEBUG] my_apic_id:0x21 cpu_index: 0x6 [DEBUG] my_apic_id:0x40 cpu_index: 0x6 [DEBUG] my_apic_id:0x31 cpu_index: 0x6 [DEBUG] my_apic_id:0x39 cpu_index: 0x6 [DEBUG] my_apic_id:0xa cpu_index: 0x3 [DEBUG] my_apic_id:0x0 cpu_index: 0x0 [DEBUG] my_apic_id:0x8 cpu_index: 0x2 [DEBUG] my_apic_id:0x4 cpu_index: 0x2 [DEBUG] my_apic_id:0x28 cpu_index: 0x6 [DEBUG] my_apic_id:0x2 cpu_index: 0x1 [DEBUG] my_apic_id:0x38 cpu_index: 0x6 [DEBUG] my_apic_id:0x29 cpu_index: 0x6 [DEBUG] my_apic_id:0xe cpu_index: 0x5 [DEBUG] my_apic_id:0x6 cpu_index: 0x2 [DEBUG] my_apic_id:0x20 cpu_index: 0x6 [DEBUG] my_apic_id:0x30 cpu_index: 0x6 [DEBUG] my_apic_id:0x19 cpu_index: 0x6 [DEBUG] my_apic_id:0xc cpu_index: 0x4 [DEBUG] my_apic_id:0x18 cpu_index: 0x6 We can see same cpu_index for multiple cores before fix. After this patch.. [DEBUG] my_apic_id:0x10 cpu_index: 0x8 [DEBUG] my_apic_id:019 cpu_index: 0xb [DEBUG] my_apic_id:0x11 cpu_index: 0x9 [DEBUG] my_apic_id:0x18 cpu_index: 0xa [DEBUG] my_apic_id:0x40 cpu_index: 0x14 [DEBUG] my_apic_id:0x30 cpu_index: 0x10 [DEBUG] my_apic_id:0x42 cpu_index: 0x15 [DEBUG] my_apic_id:0xc cpu_index: 0x6 [DEBUG] my_apic_id:0x2 cpu_index: 0x1 [DEBUG] my_apic_id:0x29 cpu_index: 0xf [DEBUG] my_apic_id:0xe cpu_index: 0x7 [DEBUG] my_apic_id:0x20 cpu_index: 0xc [DEBUG] my_apic_id:0x0 cpu_index: 0x0 [DEBUG] my_apic_id:0x31 cpu_index: 0x11 [DEBUG] my_apic_id:0x28 cpu_index: 0xe [DEBUG] my_apic_id:0x21 cpu_index: 0xd [DEBUG] my_apic_id:0xa cpu_index: 0x5 [DEBUG] my_apic_id:0x38 cpu_index: 0x12 [DEBUG] my_apic_id:0x8 cpu_index: 0x4 [DEBUG] my_apic_id:0x4 cpu_index: 0x2 [DEBUG] my_apic_id:0x39 cpu_index: 0x13 Change-Id: I69e5e6231dd18b43d439340aaed50eb9edeca3b7 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70751 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-08soc/intel/common: Untie PRMRR from SGXPratikkumar Prajapati
PRMRR is used by many Intel SOC features, not just Intel SGX. As of now SGX and Key Locker are the features that need PRMRR. Untie it from Intel SGX specific files and move to common cpulib. Also rename PRMRR size config option. Use the renamed PRMRR size config option to set the PRMRR size. TEST=Able to set PRMRR size using config. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: I0cd49a87be0293530705802fd9b830201a5863c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70819 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-01-06soc/intel/: Rename small and big cores referencesSridhar Siricilla
The patch addresses Intel heterogeneous cores as `Efficient` and `Performance` cores instead of `small` and `big` cores. It is to ensure coreboot code has uniform reference to the heterogeneous cores. So, the patch renames all `small` and `big` core references to `efficient` (eff) and `performance` (perf) cores respectively. TEST=Build the code for Brya and Rex boards Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I98c9c0ed86b211d736a0a1738b47410faa13a39f Reviewed-on: https://review.coreboot.org/c/coreboot/+/71639 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-01-06soc/intel/common: Check PRMRR dependent featuresPratikkumar Prajapati
Add below mentioned functions: is_sgx_configured_and_supported(): Checks if SGX is configured and supported is_keylocker_configured_and_supported(): Checks if Key Locker is configured and supported check_prm_features_enabled(): Checks if any of the features that need PRM are configured and supported. As of now SGX and Key Locker are the only features that need PRM. Also, call check_prm_features_enabled() from get_valid_prmrr_size() to make sure PRM dependent features are enabled and configured before returning PRMRR size. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: I51d3c144c410ce4c736f10e3759c7b7603ec3de9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-06soc/intel/common: Add Kconfig option for Intel Key LockerPratikkumar Prajapati
Add INTEL_KEYLOCKER Kconfig option. Disable it by default. The specification of Key Locker can be found via document #343965 on Intel's site. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: Ia78e9bfe7ba2fd4e45b4821c95b19b8e580dccab Reviewed-on: https://review.coreboot.org/c/coreboot/+/71118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-01-06soc/intel/common: Use CPUID_STRUCT_EXTENDED_FEATURE_FLAGS macroPratikkumar Prajapati
Use CPUID_STRUCT_EXTENDED_FEATURE_FLAGS macro to get extended CPU capabilities flags using cpuid_ext inline function. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: If680ffff64e2e1dabded8c03c4042d349a11b635 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71646 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-04soc/intel: Create common function to check PCH slotKapil Porwal
BUG=none TEST=Build and boot to google/taniks. Check dmesg and make sure that there is no regression. Also confirm that there is no change in ACPI _PRT and IO-APCI interrupt assignment. IO-APIC interrupts before and after this patch: 1: IO-APIC 1-edge i8042 8: IO-APIC 8-edge rtc0 9: IO-APIC 9-fasteoi acpi 14: IO-APIC 14-fasteoi INTC1055:00 23: IO-APIC 23-fasteoi idma64.5, ttyS0 37: IO-APIC 37-fasteoi idma64.0, i2c_designware.0 38: IO-APIC 38-fasteoi idma64.1, i2c_designware.1 40: IO-APIC 40-fasteoi idma64.2, i2c_designware.2 41: IO-APIC 41-fasteoi idma64.3, i2c_designware.3 42: IO-APIC 42-fasteoi idma64.4, i2c_designware.4 45: IO-APIC 45-fasteoi idma64.6, pxa2xx-spi.6 77: IO-APIC 77-edge cr50_i2c 100: IO-APIC 100-fasteoi ELAN0000:00 103: IO-APIC 103-fasteoi chromeos-ec _PRT before and after this patch: Package (0x04) ==> 0x0001FFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x0002FFFF, 0x00, 0x00, 0x00000011 Package (0x04) ==> 0x0004FFFF, 0x00, 0x00, 0x00000012 Package (0x04) ==> 0x0005FFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x0006FFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x0006FFFF, 0x02, 0x00, 0x00000012 Package (0x04) ==> 0x0007FFFF, 0x00, 0x00, 0x00000013 Package (0x04) ==> 0x0007FFFF, 0x01, 0x00, 0x00000014 Package (0x04) ==> 0x0007FFFF, 0x02, 0x00, 0x00000015 Package (0x04) ==> 0x0007FFFF, 0x03, 0x00, 0x00000016 Package (0x04) ==> 0x0008FFFF, 0x00, 0x00, 0x00000017 Package (0x04) ==> 0x000DFFFF, 0x00, 0x00, 0x00000011 Package (0x04) ==> 0x000DFFFF, 0x01, 0x00, 0x00000013 Package (0x04) ==> 0x0010FFFF, 0x00, 0x00, 0x00000018 Package (0x04) ==> 0x0010FFFF, 0x01, 0x00, 0x00000019 Package (0x04) ==> 0x0010FFFF, 0x02, 0x00, 0x00000014 Package (0x04) ==> 0x0010FFFF, 0x03, 0x00, 0x00000015 Package (0x04) ==> 0x0011FFFF, 0x00, 0x00, 0x0000001A Package (0x04) ==> 0x0011FFFF, 0x01, 0x00, 0x0000001B Package (0x04) ==> 0x0011FFFF, 0x02, 0x00, 0x0000001C Package (0x04) ==> 0x0011FFFF, 0x03, 0x00, 0x0000001D Package (0x04) ==> 0x0012FFFF, 0x00, 0x00, 0x0000001E Package (0x04) ==> 0x0012FFFF, 0x01, 0x00, 0x0000001F Package (0x04) ==> 0x0012FFFF, 0x02, 0x00, 0x00000016 Package (0x04) ==> 0x0013FFFF, 0x00, 0x00, 0x00000020 Package (0x04) ==> 0x0013FFFF, 0x01, 0x00, 0x00000021 Package (0x04) ==> 0x0013FFFF, 0x02, 0x00, 0x00000022 Package (0x04) ==> 0x0013FFFF, 0x03, 0x00, 0x00000023 Package (0x04) ==> 0x0014FFFF, 0x01, 0x00, 0x00000017 Package (0x04) ==> 0x0014FFFF, 0x00, 0x00, 0x00000024 Package (0x04) ==> 0x0014FFFF, 0x02, 0x00, 0x00000011 Package (0x04) ==> 0x0015FFFF, 0x00, 0x00, 0x00000025 Package (0x04) ==> 0x0015FFFF, 0x01, 0x00, 0x00000026 Package (0x04) ==> 0x0015FFFF, 0x02, 0x00, 0x00000027 Package (0x04) ==> 0x0015FFFF, 0x03, 0x00, 0x00000028 Package (0x04) ==> 0x0016FFFF, 0x00, 0x00, 0x00000012 Package (0x04) ==> 0x0016FFFF, 0x01, 0x00, 0x00000013 Package (0x04) ==> 0x0016FFFF, 0x02, 0x00, 0x00000014 Package (0x04) ==> 0x0016FFFF, 0x03, 0x00, 0x00000015 Package (0x04) ==> 0x0017FFFF, 0x00, 0x00, 0x00000016 Package (0x04) ==> 0x0019FFFF, 0x00, 0x00, 0x00000029 Package (0x04) ==> 0x0019FFFF, 0x01, 0x00, 0x0000002A Package (0x04) ==> 0x0019FFFF, 0x02, 0x00, 0x0000002B Package (0x04) ==> 0x001CFFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x001CFFFF, 0x01, 0x00, 0x00000011 Package (0x04) ==> 0x001CFFFF, 0x02, 0x00, 0x00000012 Package (0x04) ==> 0x001CFFFF, 0x03, 0x00, 0x00000013 Package (0x04) ==> 0x001DFFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x001DFFFF, 0x01, 0x00, 0x00000011 Package (0x04) ==> 0x001DFFFF, 0x02, 0x00, 0x00000012 Package (0x04) ==> 0x001DFFFF, 0x03, 0x00, 0x00000013 Package (0x04) ==> 0x001EFFFF, 0x00, 0x00, 0x00000017 Package (0x04) ==> 0x001EFFFF, 0x01, 0x00, 0x00000014 Package (0x04) ==> 0x001EFFFF, 0x02, 0x00, 0x0000002C Package (0x04) ==> 0x001EFFFF, 0x03, 0x00, 0x0000002D Package (0x04) ==> 0x001FFFFF, 0x01, 0x00, 0x00000016 Package (0x04) ==> 0x001FFFFF, 0x02, 0x00, 0x00000017 Package (0x04) ==> 0x001FFFFF, 0x03, 0x00, 0x00000014 Package (0x04) ==> 0x001FFFFF, 0x00, 0x00, 0x00000015 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ib4fc850228b7ddbf84e2feb2433adff5e4002033 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71236 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-04soc/intel/common/block/fast_spi: Hook up pci_dev_ops_pci to set SSIDKapil Porwal
BUG=none TEST=Verify presence of subsystem ID for fast_spi device on google/rex. lspci output before this patch: 00:1f.5 Serial bus controller [0c80]: Intel Corporation Device [8086:7e23] lspci output after this patch: 00:1f.5 Serial bus controller [0c80]: Intel Corporation Device [8086:7e23] Subsystem: Intel Corporation Device [8086:7e23] Note: UPD SiSkipSsidProgramming was set to 1 for above test. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I08c7a5a3fdc7389b315e85180c16d1ec335fbba2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-01-04soc/intel/common: Add API to check Key Locker supportPratikkumar Prajapati
Add is_keylocker_supported() API in common cpulib. This function checks if the CPU supports Key Locker feature. Returns true if Key Locker feature is supported otherwise false. Change-Id: Ide9e59a4f11a63df48838eab02c2c584cced12e1 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71117 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-02soc/intel/common: Move SGX supported API to cpulibPratikkumar Prajapati
Move is_sgx_supported() API to common cpulib code, so that this function can be used by other code without enabling SOC_INTEL_COMMON_BLOCK_SGX_ENABLE config option. Change-Id: Ib630ac451152ae2471c862fced992dde3b49d05d Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-12-27tree/acpi: Replace constant "Zero" with actual numberFelix Singer
Change-Id: I5a3e3506415f424bf0fdd48fc449520a76622af5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71525 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-25soc/intel: Move max speed API to commonDinesh Gehlot
This patch moves API "smbios_cpu_get_max_speed_mhz()" to common code from board specific. This API was made generic in 'commit d34364bdea12 ("soc/intel/alderlake: Utilize `CPU_BCLK_MHZ` over dedicated macro")' BUG=NONE TEST=Boot and verified that SMBIOS max speed value is correct on brya and rex. (brya) dmidecode -t : "Max Speed: 4400 MHz" (rex) dmidecode -t : "Max Speed: 3400 MHz" Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I87040ab23319097287e191d7fc9579f16d716e62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70879 Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23soc/intel/cmn/block/pmc: Add pmc_or_mmio32 utility functionTim Chu
Change-Id: I5f9845dd3ea098d990710eaaa2d5db495f876cdd Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22soc/intel/alderlake: Add Raptor Lake device IDsMarx Wang
Add system agent ID for RPL QDF#Q2MB/Q2PS TEST=able to build coreboot successfully Signed-off-by: Marx Wang <marx.wang@intel.com> Change-Id: I169c8bc51cdf7fbfcdb1996d93afa4a352e2fddf Reviewed-on: https://review.coreboot.org/c/coreboot/+/71121 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-20soc/intel/cmn/block/cnvi: Add missing CNVI IDs for ADLKapil Porwal
Add missing CNVI IDs for ADL - ADL-P: 0x51f2, 0x51f3 ADL-S: 0x7af1, 0x7af2, 0x7af3 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I189be9a8c8895a93d98886e6591e771bbce5f564 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-12-20soc/intel/*/crashlog.[ch]: Remove unused includesElyes Haouas
Change-Id: I126d49c27302e1ed2e00ff491d59cadda7101d12 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70924 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-20src/soc: Remove unneeded <assert.h>Elyes Haouas
As _Static_assert() is a compiler built-in, <assert.h> is not needed. Change-Id: I578b4bf286538d0606569d19ec760a1846c8145b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-17soc/intel/cmn: Clear interrupt status after HECI-1 has been receivedJohnny Lin
According to Intel doc#630774, BIOS should clear Host Interrupt Status if it has read all the slots of the message from the ME circular buffer. Since this is not found in client ME document, add a Kconfig SOC_INTEL_CSE_SERVER_SKU that only clears interrupt status for Server ME SKU. On SPR-SP, if mainboard calls get_me_fw_version via HECI-1, with the change can avoid seeing below Linux warning during boot with Linux v5.12: [ 17.868929] irq 16: nobody cared (try booting with the "irqpoll" option) [ 17.883819] CPU: 10 PID: 0 Comm: swapper/10 Not tainted 5.12.0 [ 17.902412] Hardware name: Wiwynn Crater Lake EVT2/Crater Lake-Class1 [ 17.922327] Call Trace: [ 17.927780] <IRQ> [ 17.932253] dump_stack+0x64/0x7c [ 17.939640] __report_bad_irq+0x37/0xb1 [ 17.948206] note_interrupt.cold.11+0xa/0x63 [ 17.957713] handle_irq_event_percpu+0x6a/0x80 [ 17.967626] handle_irq_event+0x2a/0x50 [ 17.976163] handle_fasteoi_irq+0x9e/0x140 [ 17.985305] __common_interrupt+0x38/0x90 [ 17.994255] common_interrupt+0x7a/0xa0 [ 18.002821] </IRQ> [ 18.007514] asm_common_interrupt+0x1e/0x40 Change-Id: I1cf21112870e53a11134d43e461b735ead239717 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2022-12-17soc/intel/common: Remove read-only from chip_get_common_soc_structureSean Rhodes
Remove the `const` property from chip_get_common_soc_structure so that the returned values can be overwritten as required. Cc: th3fanbus@gmail.com Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I7d3db0bc119cd9b9b276abd68754e750e06a788c Reviewed-on: https://review.coreboot.org/c/coreboot/+/70774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-16cpu/intel: Fix clearing MTRR for clang 64bitArthur Heymans
Clang generates R_X86_64_32S symbols that get truncated. TESTED: - prodrive/hermes boots with GCC and clang - MTRR are properly cleared (tested by filling in both MTRR_FIX_64K_00000 and MTRR_FIX_4K_F8000 before clearing) Change-Id: I6a5139f7029b6f35b44377f105dded06f6d9cbf9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-16soc/intel/common: Drop unreferenced DP related macrosSridhar Siricilla
The patch drops the unreferenced DP related timeout macros. TEST=Build code for Rex Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I3f4c7733a92d1b7cb107410fedaca20ede040050 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-15soc/intel/{adl, common}: provide a list of D-states to enter LPMEran Mitrani
This was done previously for ADL. moving the code to common so it can be leveraged for other platforms (e.g. MTL) TEST=Built and tested on anahera by verifying SSDT contents Change-Id: I45eded3868a4987cb5eb0676c50378ac52ec3752 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-15treewide: Remove unused 'include <arch/io.h>'Elyes Haouas
Change-Id: I6f1d7625eb457084ba893b25518fdfdb59cf64db Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-12-15soc/intel/{adl, cmn/pcie}: Fix ASPM configuration enum definitionsSubrata Banik
As per PCI Express Base Specification 5.0 section 5.4.1.3 ASPM Configuration +-----------------------+-------------------------------+ | Field Description | ASPM Support | +-----------------------+-------------------------------+ | 00b | No ASPM support | +-----------------------+-------------------------------+ | 01b | L0s Supported | +-----------------------+-------------------------------+ | 10b | L1 Supported | +-----------------------+-------------------------------+ | 11b | L0s and L1 Supported | +-----------------------+-------------------------------+ 100b aka 0x4 is added by FSP to allow auto configuration (to avoid conflicting with the PCI specification defined values). Additionally, changed enum definition which is now meeting the FSP expectations better. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8c9055f721e144f2ff5055e5f99ea641efc4d268 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70719 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-14soc/intel/common: Add helper function to get DP modeSridhar Siricilla
The patch adds helper function to get the DP mode. TEST=Build the code for Rex Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I02ed1f818e77c37ead8ce962fa12fddfdc8efeb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-13soc/intel/common/block: add definition of GPIO configurationJeff Li
Add two macros: - PAD_CFG_NF_OWNERSHIP() - PAD_CFG_GPIO_OWNERSHIP() to support setting the Host Software Ownership (own) fields. Signed-off-by: lichenchen.carl <lichenchen.carl@bytedance.com> Change-Id: Ia3f2ad8658b751156456b69366fa4b1badb8b595 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70421 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-12-13soc/intel/cmn/tcss: Skip sending CONN IPC command during S3 resumeSubrata Banik
This patch skips sending CONN IPC command to PMC if system is resuming from S3. Sending CONN IPC command as part of `tcss_configure_dp_mode()` function results into ERROR while system is resuming from S3. Additionally, skip `configure_aux_bias_pads()` during S3 resume. BUG=b:260984500 TEST=Able to test on Google/Rex. Without this patch: [ERROR] pmc_send_ipc_cmd status: fatal [ERROR] Port 1 connect request failed [SPEW ] [TCSS] TcssInit() - End With this patch: No error seen during S3 resume. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1dab7dc8b4ad76ca0c9630456803c1b9a320fe40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-12drivers/wifi: Move ADL-P CNVi IDs from generic to IA common code CNVi driverKapil Porwal
BUG=b:259716145 TEST=Dump SSDT and see that _PRW and _DSD for CNVi device contains the value from the devicetree on google/redrix. Before: Scope (\_SB.PCI0.WFA3) { Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x6D, 0x03 }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"), Package (0x01) { Package (0x02) { "DmaProperty", One } } }) ... } After: Scope (\_SB.PCI0.CNVW) { Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x6D, 0x03 }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"), Package (0x01) { Package (0x02) { "DmaProperty", One } } }) ... } Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ia4ffedcb53afe350694eb03a144d12f714190cc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70447 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10soc/intel: Move TCSS FW latency macros to IA common tcss.hSubrata Banik
This patch moves TCSS firmware latency related macros from SoC specific tcss.h to IA common tcss.h Additionally, ensure other structure definitions belonging to the IA common code tcss.h are not causing compilation issues for ASL files (due to including FW latency macros) hence, guarded against `!defined(__ACPI__)`. TEST=Able to build and boot Google/Rex and Google/Kano. Change-Id: Id51545ef714979c6ba09a2b468231b1f4bab0be7 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70487 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-07mb,sb,soc/intel: Drop useless IO trap handlersKyösti Mälkki
There are four requirements for the SMI to hit a printk() this commit now removes. Build must have DEBUG_SMI=y, otherwise any printk() is a no-op inside SMM. ASL must have a TRAP() with argument 0x99 or 0x32 for SMIF value. Platform needs to have IO Trap #3 enabled at IO 0x800. The SMI monitor must call io_trap_handler for IO Trap #3. At the moment, only getac/p470 would meet the above criteria with TRAP(0x32) in its DSDT _INI method. The ASL ignores any return value of TRAP() calls made. A mainboard IO trap handler should have precedence over a southbridge IO trap handler. At the moment we seem to have no cases of the latter to support, so remove the latter. Change-Id: I3a3298c8d9814db8464fbf7444c6e0e6ac6ac008 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-12-07sb,soc/intel: Fix SMI handler IO trap data maskKyösti Mälkki
Shift is done in multiples of 8 (1 << 3) bits. It was fixed already for i82801ix/jx. Change-Id: I5e1c2b3bf4ba68f34eb43e59fe783d5cd6e0a39a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-06soc/intel/common/block: Use readXXp/writeXXp()Elyes Haouas
Change-Id: I83d05ce0b26b01fdfc95d1442a4c930ed77bf25c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06soc/intel/xeon_sp: Read ioapic configuration from hardwareArthur Heymans
This is more robust than hardcoding whathever FSP has set up and is a lot less code. Change-Id: I6423ddc139d742879d791b054ea082768749c0a7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70265 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-06soc/intel/alderlake: make SOC_INTEL_CSE_SEND_EOP_EARLY per-board configurableMichał Kopeć
SOC_INTEL_CSE_SEND_EOP_EARLY breaks soft ME disable, which works using a HECI message that needs to be sent before EOP. Make the option configurable to allow soft ME disable on alderlake. Change-Id: I7febf7c029e7eac94052cc3a8142949d6813c1bc Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-06util/cbfstool: Add a new mechanism to provide a memory mapArthur Heymans
This replaces the mechanism with --ext-win-base --ext-win-size with a more generic mechanism where cbfstool can be provided with an arbitrary memory map. This will be useful for AMD platforms with flash sizes larger than 16M where only the lower 16M half gets memory mapped below 4G. Also on Intel system the IFD allows for a memory map where the "top of flash" != "below 4G". This is for instance the case by default on Intel APL. TEST: google/brya build for chromeos which used --ext-win-base remains the same after this change with BUILD_TIMELESS=1. Change-Id: I38ab4c369704497f711e14ecda3ff3a8cdc0d089 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-12-05soc/intel/common/block/uart: Show ACPI UART in OSAngel Pons
Do not hide UARTs in ACPI mode from the OS, as this prevents using them on at least Windows. Currently, the driver is only used on the Prodrive Hermes mainboard. Change-Id: I01bdccff1b11e1862970c924fd5fc7718a2d6ce9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70155 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05soc/intel/cmn/block/{pcie/rtd3,usb4}: Use helper functions for _DSDKapil Porwal
BUG=b:259716145 TEST=Verified SSDT on google/rex. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ib57dea9b16e4590ca2d75ac1512fdaf773ec50f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70065 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02soc/intel/cmn/cse: Allow to perform essential CSE operations post EOPSubrata Banik
This patch allows to send late EOP cmd to CSE (after CSE .final) using boot state machine (either BS_PAYLOAD_BOOT or BS_PAYLOAD_LOAD) if the SoC user selects SOC_INTEL_CSE_SEND_EOP_LATE config. Rename `set_cse_end_of_post()` to `send_cse_eop_with_late_finalize()` to make the function name more meaningful with its operation. BUG=b:260041679 TEST=Able to boot Google/Rex after sending CSE EOP late. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: If4c4564befcd38732368b21f1ca3e24b68c30e0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/69978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-12-02soc/intel/cmn/cse: API to perform essential CSE operations post EOPSubrata Banik
This patch creates an API that can perform essential CSE operation after sending the late EOP command to the CSE and prior booting to OS. Lists of operation are - Perform global reset lock - Put HECI1 to D0i3 and disable the HECI1 if the user selects - Set D0I3 for all HECI devices. BUG=b:260041679 TEST=Able to boot Google/Rex after sending CSE EOP late. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I10131ea9b553a62f0d632783c4dbad96d35d6563 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69977 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02soc/intel/cmn/cse: Send EOP cmd from .final aka `cse_final()`Subrata Banik
This patch refactors common code to allow cse_final() function to send EOP cmd if the SoC user selects `SOC_INTEL_CSE_SET_EOP` kconfig. This patch helps cse_final_ready_to_boot() and cse_final_end_of_firmware() function for being meaningful with its operation and let cse_final() being that outer layer to perform three operations based on the selected kconfig. 1. send cse eop command 2. perform cse_final_ready_to_boot() operations 3. perform cse_final_end_of_firmware() operations Additionally, ensures the platform that choose to send EOP late (like JSL and TGL) is not being impacted due to this code refactoring hence, skip calling into CSE.final if SoC selects `SOC_INTEL_CSE_SEND_EOP_LATE` config. BUG=b:260041679 TEST=Able to send EOP command successfully for Google/Taeko. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I412291c9378011509d3825f9b01e81bfced53303 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69975 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02soc/intel/cmn/cse: Create another config for sending CSE EOP cmd lateSubrata Banik
Presently, coreboot supports two instances of sending EOP cmd to the Intel CSE. 1. Sending EOP cmd to CSE during `.final` operation from cse pci driver. 2. Starting with Alder Lake, the recommendation was to send EOP to CSE earlier than CSE `.final` operation. Since then it's referred to as `Sending EOP Early`. This method helped to save the CSE EOP response time significantly. During Meteor Lake platform, CSE EOP response time has become non-deterministic and we have figured that sending EOP command later than CSE .final operation is actually helping to optimize the boot time significantly (around ~150ms savings compared to sending from `.final` ops and ~5sec compared to sending CSE early). Hence, this patch intended to create yet another kconfig for sending CSE late (specifically after `.final` operation). The idea for this newer config is to use the boot state machine for sending CSE EOP cmd. The patch train in this series would add the specific changes to allow sending EOP late and perform other essential operations required prior booting to OS as coreboot decided to skip calling into FSP Notify phase. Starting with Jasper Lake, coreboot sends EOP before loading payload hence, this config is applicable for those platforms. The current plan is that Intel Jasper Lake, Tiger Lake and Meteor Lake platform will select this newer config from SoC code. BUG=b:260041679 TEST=Able to send EOP command successfully for Google/Taeko. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iea512cd5b79d61dd5d5a962079baf525027c831f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69976 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-29soc/intel/cmn/block/pcie/rtd3: Add support for ACPI DmaPropertyKapil Porwal
BUG=b:259716145 TEST=Verified SSDT on google/rex. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I921b06e8d35ddac0bc8175b13a33c84515b282a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70028 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-29{soc/intel/cmn/pcie, mb/google/volteer}: Rename `is_external` variableKapil Porwal
Name a variable based on its utility. `is_external` variable adds `ExternalFacingPort` _DSD property to an ACPI device hence rename it to `add_acpi_external_facing_port`. BUG=b:259716145 TEST=Build google/rex with this flag and verify it in SSDT at runtime. SSDT snippet: Name (_DSD, Package (0x04) // _DSD: Device-Specific Data { ToUUID ("6211e2c0-58a3-4af3-90e1-927a4e0c55a4"), Package (0x01) { Package (0x02) { "HotPlugSupportInD3", One } }, ToUUID ("efcc06cc-73ac-4bc3-bff0-76143807c389"), Package (0x01) { Package (0x02) { "ExternalFacingPort", One } } }) Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I65100283ed9b65037c9890f28ecab41fcfa25d83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69970 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-28sb,soc/intel: Address TCO SECOND_TO_STS name collisionKyösti Mälkki
Later soc/intel/common/smbus addresses TCO2_STS as a separate 16-bit register, while baytrail and braswell assumes 32-bit wide TCO1_STS to extend as TCO2_STS. In src/soc/intel/denverton_ns: #define TCO2_STS_SECOND_TO 0x02 In soc/intel/baytrail,braswell: #define SECOND_TO_STS (1 << 17) Elsewehere #define SECOND_TO_STS (1 << 1) It's expected that we remove the first (1 << 17) case and only access TCO2_STS as a separate 16-bit register. For now, use unique names to avoid confusion. Change-Id: I07cc46a9d600b2bf2f23588b26891268e9ce4de0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-26src/soc/intel: Remove unnecessary space after castsElyes Haouas
Change-Id: I098104f32dd7c66d7bb79588ef315a242c3889ba Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-26soc/intel/cmn/cse: Create API to get CSE Lite WP InformationSubrata Banik
This patch creates an API for CSE-Lite specific SKU to retrieve the Write Protect (WP) information (`cse_log_ro_write_protection_info`) like WP range and limit, if the region is write-protected or not etc. BUG=none TEST=Able to compile the cse_lite.c file for google/kano without any error. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8f4b7880534ded5401b6f8d601ded88019c636c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69968 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-25ACPI: Use common code for MADT LAPIC NMIsKyösti Mälkki
Use the broadcast ID to deliver LINT1 as NMI to all CPUs, instead of listing individual LAPIC IDs. Change-Id: Iaf714d8c2aabd16c59c3bcebc4a207406fc85ca9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-23soc/intel/common: Define post codesMartin Roth
For the most part, this just moves the existing post codes into macros so that they're not just bare numbers. cache_as_ram.S: Post code 0x28 was previously pointless with just a single jump between it and post code 0x29, car_init_done. This code was removed, and the 0x28 value was used to differentiate the car_nem_enhanced subroutine from the other 0x26 post codes used before calling the clear_car subroutine. All other post codes remain identical. POST_BOOTBLOCK and POST_CODE_ZERO are expected to become global, whereas the POST_SOC codes are expected to be Intel only. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I82a34960ae73fc263359e4519234ee78e7e3daab Reviewed-on: https://review.coreboot.org/c/coreboot/+/69865 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-19soc/intel/common: Fix the TCSS DisplayPort detection flowzhaojohn
After DisplayPort is plugged into type-C port, its hpd signal instantly presents and EC has mux_info for dp and hpd. This change fixes the DP detection flow to avoid the 1 second delay while no DP is connected. If DP is present, there will be requests towards PMC through the sequence of connect, safe mode, dp and hpd mode. BUG=b:247670186 TEST=Built image and validated the DisplayPort preboot feature on Rex. Change-Id: I7cb95ec7fcc7e1a86e86466e6d45390eedcc4531 Signed-off-by: zhaojohn <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-18soc/intel/meteorlake: Add Meteor Lake MCH device IDSridhar Siricilla
Add Meteor Lake MCH device ID 0x7d15. TEST=Build and verify boot on MTL RVP With patch, coreboot log: `[DEBUG] MCH: device id 7d15 (rev 00) is Meteorlake P` Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: If46b01910239173cd74bf6eebc69a81291b6e15a Reviewed-on: https://review.coreboot.org/c/coreboot/+/69560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-17soc/intel/common/block/sgx/Kconfig: Add missing default symbolElyes Haouas
default SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE value is missing by accident for SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_32MB. Change-Id: Ib3af0a1c509ab2e2eccf3e36ff604a1040995af4 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69332 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-15soc/intel: Add Meteor Lake IGD device id 0x7d45Ravi Sarawadi
Add new IGD device. Reference: EDS Vol 1 (640228) Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.corp-partner.google.com> Change-Id: Iad69f547a981390ef3749256e9fd9bcfc106fe3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-12include/cpu/msr.h: transform into an unionArthur Heymans
This makes it easier to get the content of an msr into a full 64bit variable. Change-Id: I1b026cd3807fd68d805051a74b3d31fcde1c5626 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68572 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-10sb,soc/intel: Use register_new_ioapic_gsi0()Kyösti Mälkki
Change-Id: I6b0e4021595fb160ae3bf798468f4505b460266f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-10sb,soc/intel: Use acpi_create_madt_ioapic_from_hw()Kyösti Mälkki
Change-Id: I9fd9cf230ce21674d1c24b40f310e5558e65be25 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-09device/xhci: Factor out `struct xhci_usb_info`Robert Zieba
This commit factors out `struct xhci_usb_info` from intel specific code as it will be useful on other platforms. BUG=b:186792595 TEST=Builds for volteer Change-Id: I5b4cc6268f072c6948f11c7498a564d7a5c0a190 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-11-09device/xhci: Factor out common PORTSC codeRobert Zieba
This commit factors out some code for XHCI port status values. BUG=b:186792595 TEST=Built coreboot for volteer device Change-Id: I045405ed224aa8f48f6f628b7d49ec6bafb450d7 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-09soc/intel/common/xhci: Fix building for 64bitArthur Heymans
Tested with clang on prodrive/hermes: Boots to payload Change-Id: I66392bcb4ed94c97dde43342dd29dab15d1dd9ea Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69234 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-08vboot: Introduce handy vboot reboot functionsJakub Czapiga
This patch groups vboot context, recovery reason and subcode saving, and reboot calls into two handy functions: - vboot_save_and_reboot() - save context and reboot - vboot_fail_and_reboot() - store recovery reason and call function above Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ie29410e8985e7cf19bd8d4cccc393b050ca1f1c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69208 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-11-07soc/intel/common/block/pcie/rtd3: Skip Power On if _STA returns 1Kane Chen
RTD3,_ON method sometimes can create delays during system boot. Even when the power is already up, kernel still tries to call _ON method to power up device, but it's unnecessary. RTD3._STA returns device power, so _ON method can check _STA and see if the power on process can be skipped BUG=b:249931687 TEST=system can boot to OS with RTD3 pcie storage and save ~80 ms on Crota. Suspend stress test passes 100 cycles Change-Id: I296ce1b85417a5dbaca558511cd7fc51a3a38c84 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-05soc/intel/block/power_limit: Avoid MSR read if it is not neededWerner Zeh
In function 'set_power_limits' there is a path to bail out early if the Kconfig switch SOC_INTEL_DISABLE_POWER_LIMITS is selected. In this case reading the MSR PLATFORM_INFO is useless and can be avoided. So read it right before the value is needed. This was found by the scanbuild. In addition, fix an unnecessary line break to increase code readability. Change-Id: Ibdededdfd56287fb9b9223e78033a3cd6425e1a2 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-04soc/intel: Include <cpu/cpu.h> instead of <arch/cpu.h>Elyes Haouas
Also sort includes. Change-Id: I7da9c672ee230dfaebd943247639b78d675957e4 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-11-04soc/intel/**/fast_spi.c: Drop spurious whitespaceAngel Pons
Drop 1 (one) newline and 1 (one) space. Change-Id: I1972d173f99507dd167bd86c73d99434b04701ab Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69167 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-02soc/intel/common: provide display hook in PEP for ECsMichael Niewöhner
Provide PEP display notification hook for ECs. Change-Id: Icbfd294cdd238e63eb947c227a9cf73daca702ef Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-31soc: Add SPDX license headers to MakefilesMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic875708697f07b6dae09d27dbd67eb8b960749f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-10-27Revert "soc/intel/systemagent.c: Fix memory type reporting"Arthur Heymans
This reverts commit 9c2f3cc9d9b3b3b7cfe1e62a70ea3061ca6c15ac. This broke the smihandler for no clear reason on some platforms. Change-Id: I72da99c019241b627ce8b543937364a53a5fe97b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-10-27soc/intel/{adl,cmn}: Add/Remove LTR disqualification for UFSMeera Ravindranath
a) Add LTR disqualification in D3 to ensure PMC ignores LTR from UFS IP as it is infinite. b) Remove LTR disqualification in _PS0 to ensure PMC stops ignoring LTR from UFS IP during D3 exit. c) Add Kconfig (SOC_INTEL_UFS_LTR_DISQUALIFY) check to apply this LTR WA. BUG=b:252975357 TEST=build and boot nirwen and see no issues in PLT runs Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I88772b0b7dde1fca0130472a38628e72dfd6c26c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-10-27soc/intel/{adl, cmn}: Allow config to select the OCP workaroundSubrata Banik
This patch introduces a config option for SoC code to choose the applicable SoC workaround. For now, we have introduced `SOC_INTEL_UFS_OCP_TIMER_DISABLE` to apply UFS OCP timeout disable workaround. At present ADL SoC only selects so, and in future MTL and others should check with Intel prior selecting this kconfig. It's the placeholder to add more workaround in required going forward. BUG=none TEST=Able to build and boot Google/Brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia2364d2de9725256dfa2269f2feb3d892c52086a Reviewed-on: https://review.coreboot.org/c/coreboot/+/68309 Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-10-25soc/intel/alderlake: Add Raptor Lake device IDsLawrence Chang
Add system agent ID for RPL QDF# Q271 TEST=Tested by ODM and "MCH: device id a71b (rev 01) is Unknown" msg is gone Signed-off-by: Lawrence Chang <lawrence.chang@intel.corp-partner.google.com> Change-Id: I6fd51d9915aa59d012c73abc2477531643655e54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kane Chen <kane.chen@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-10-25soc/intel/common: Clean up includesElyes Haouas
Change-Id: I0081fcf3c842d8772a7045f8dc5754a2e6c039b8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-22soc/intel/systemagent: Rewrite using new resource APIArthur Heymans
Working with resources in KB is tedious and the base_k / size_k variable naming was simply wrong in one case. Change-Id: Ic5df054e714d06c9003752ed49dc704554e7b904 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68406 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-22soc/intel/systemagent.c: Fix memory type reportingArthur Heymans
TOLUD stands for top of lower usable dram. Memory between cbmem_top and TOLUD, even if stolen for another device/purpose can still be marked WB cacheable. This will result in a cleaner MTRR setup. Change-Id: Ic3d6f589c60e44a3dce9122d206397cac968647f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68405 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-20soc/intel/cmn/block/acpi: Create common ASL entry for UFSSubrata Banik
This patch migrates UFS ASL entry from Alder Lake SoC to common block ACPI code to be able to be utilized across different IA SoCs. Additionally, migrate to ASL2.0. BUG=none TEST=Able to build and boot Google/Kano. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I2e803138a20fd1fc3cdcd5c0fbbb1254663bb8dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/68300 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-14 09:04:42 +0000