| Age | Commit message (Expand) | Author |
|---|
| 2021-03-27 | soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.h | Subrata Banik |
| 2021-03-20 | soc/intel: Drop unused `GPIO_NUM_GROUPS` macro | Angel Pons |
| 2021-03-01 | soc/intel: Drop `bootblock_cpu_init()` function | Angel Pons |
| 2021-03-01 | soc/intel/{skl,cnl}: Do not chain-include systemagent.h | Angel Pons |
| 2021-03-01 | soc/intel: Drop `romstage_pch_init()` function | Angel Pons |
| 2021-03-01 | soc/intel: Factor out common smbus.h | Angel Pons |
| 2021-03-01 | soc/intel: Factor out common gpe.h | Angel Pons |
| 2021-02-25 | soc/intel/{skl,cnl}: Uniformize romstage.h whitespace | Angel Pons |
| 2021-02-16 | soc/intel: Drop aliases on MMCONF_BASE_ADDRESS | Kyösti Mälkki |
| 2021-01-24 | soc/intel/cnl: use Kconfig to determine PCH type | Michael Niewöhner |
| 2021-01-21 | soc/intel/cannonlake: Allow RP#1 usage for ClkSrc | Jeremy Soller |
| 2021-01-11 | soc/intel/cnl: add SLP_S0 residency register and enable LPIT support | Michael Niewöhner |
| 2020-12-17 | soc/intel/cannonlake: Change mainboard_silicon_init_params argument | Patrick Rudolph |
| 2020-12-04 | soc/intel/{skl,cnl}: add NMI_{EN,STS} registers | Michael Niewöhner |
| 2020-10-24 | {cpu,soc}/intel: deduplicate cpu code | Michael Niewöhner |
| 2020-10-21 | soc/intel: convert XTAL frequency constant to Kconfig | Michael Niewöhner |
| 2020-10-05 | soc: move mainboard_get_dram_part_num prototype to memory_info.h | Nick Vaccaro |
| 2020-10-05 | mb, soc: change mainboard_get_dram_part_num() prototype | Nick Vaccaro |
| 2020-10-03 | soc/intel: Make use of PMC low power program from common block | Subrata Banik |
| 2020-09-27 | soc/intel/cannonlake: Align gpio_op.asl with TGL | Subrata Banik |
| 2020-09-21 | src/soc/intel: Drop unneeded empty lines | Elyes HAOUAS |
| 2020-09-17 | soc/intel/cannonlake: add missing special function pads | Michael Niewöhner |
| 2020-09-17 | soc/intel/cannonlake: rename "RSVD" GPIOs to their correct names | Michael Niewöhner |
| 2020-09-09 | soc/intel/cannonlake: Add PCIe ports on PCH-H | Patrick Rudolph |
| 2020-07-20 | soc/intel/cannonlake: Add configs for USB 3.1 Gen2 EV settings | Jamie Chen |
| 2020-07-14 | src: Remove unused 'include <stdint.h> | Elyes HAOUAS |
| 2020-06-25 | soc/intel/cannonlake: Add missing USB_PORT_WAKE_ENABLE define | Edward O'Callaghan |
| 2020-05-26 | cannonlake: update processor power limits configuration | Sumeet R Pawnikar |
| 2020-05-14 | soc/intel: Drop ABOVE_4GB_MEM_BASE_SIZE and use cpu_phys_address_size() | Furquan Shaikh |
| 2020-05-14 | soc/intel/common/block/systemagent: Use TOUUD as base for MMIO above 4G | Furquan Shaikh |
| 2020-05-11 | treewide: Remove "this file is part of" lines | Patrick Georgi |
| 2020-05-06 | treewide: replace GPLv2 long form headers with SPDX header | Patrick Georgi |
| 2020-05-06 | treewide: Move "is part of the coreboot project" line in its own comment | Patrick Georgi |
| 2020-05-02 | acpi: Move ACPI table support out of arch/x86 (3/5) | Furquan Shaikh |
| 2020-04-06 | soc/intel/cannonlake: Use SPDX for GPL-2.0-only files | Angel Pons |
| 2020-03-18 | soc: Remove copyright notices | Patrick Georgi |
| 2020-03-07 | intel/soc: skl,apl,cnl,icl,tgl: add INTRUDER relevant registers | Michael Niewöhner |
| 2020-03-07 | intel/soc: skl,apl,cnl,icl,tgl,common: enable TCO SMIs if selected | Michael Niewöhner |
| 2020-02-25 | soc/intel/cannonlake: Add TDC config for CML | Marx Wang |
| 2020-02-17 | src/intel: Define HFSTS3 register | Sridhar Siricilla |
| 2020-02-09 | soc/intel/{common,skl,cnl,icl,apl,tgl}: Move HFSTS1 register definition to SoC | Sridhar Siricilla |
| 2020-02-04 | soc/intel: Add get_pmbase | Eugene Myers |
| 2020-02-04 | soc/intel/cannonlake: Allow Audio DSP OSC qualification for low power idle | Aamir Bohra |
| 2020-01-18 | soc/intel/cannonlake: Add chip config for SATA strength | Jamie Chen |
| 2020-01-10 | soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper | Subrata Banik |
| 2020-01-09 | sb/intel/common: Add smbus_set_slave_addr() | Kyösti Mälkki |
| 2020-01-06 | soc/intel/cannonlake: Add VR config for CFL, CNL and WHL | Patrick Rudolph |
| 2019-12-26 | soc/intel/cannonlake: Refactor pch_early_init() code | Usha P |
| 2019-12-03 | soc/intel/cannonlake: Configure GPIO PM configuration in bootblock | Subrata Banik |
| 2019-11-22 | intel/smm: Provide common smm_relocation_params | Kyösti Mälkki |
| 2019-11-10 | soc/intel/common/ebda: Drop code | Arthur Heymans |
| 2019-11-04 | soc/intel: skl,cnl,icl: rely on TOLUM as cbmem_top returned by FSP | Michael Niewöhner |
| 2019-11-01 | soc/intel/{cnl,icl}: Move globalnvs.asl/nvs.h into common/block/ | Subrata Banik |
| 2019-10-21 | Revert "soc/intel/cannonlake: Remove DMA support for PTT" | Jeremy Soller |
| 2019-08-15 | intel/smm: Define struct ied_header just once | Kyösti Mälkki |
| 2019-08-15 | soc/intel: Rename some SMM support functions | Kyösti Mälkki |
| 2019-08-15 | intel/ice,sky,cannon: Drop unused EMRR and UNCORE_EMRR code | Kyösti Mälkki |
| 2019-08-15 | mainboard/google: Fix indirect includes | Kyösti Mälkki |
| 2019-08-09 | cpu/x86/smm: Drop SMI handler address from struct | Kyösti Mälkki |
| 2019-08-08 | arch/x86: Change smm_subregion() prototype | Kyösti Mälkki |
| 2019-08-07 | cpu/x86/smm: Promote smm_subregion() | Kyösti Mälkki |
| 2019-07-25 | soc/intel: Guard remaining SA_DEV_ROOT definition | Kyösti Mälkki |
| 2019-07-21 | soc/intel: Expand SA_DEV_ROOT for ramstage | Kyösti Mälkki |
| 2019-07-17 | soc/intel: Fix regression with hidden PCI devices | Kyösti Mälkki |
| 2019-07-13 | cpu/x86: Move smm_lock() prototype | Kyösti Mälkki |
| 2019-07-10 | soc/intel: Remove invalid smm_relocate stubs | Kyösti Mälkki |
| 2019-07-07 | soc/intel/{cannonlake,icelake}: Do not define PCH_DEV_PMC in ramstage | Furquan Shaikh |
| 2019-07-07 | soc/intel/cannonlake, mb/google/sarien: Get rid of unused dev param | Furquan Shaikh |
| 2019-07-05 | soc/intel/cannonlake: Fix PMC and GPIO block values for PCH-H | Jeremy Soller |
| 2019-07-04 | soc/intel: Replace uses of dev_find_slot() | Kyösti Mälkki |
| 2019-06-03 | soc/intel: Replace UART_BASE() and friends with a Kconfig | Nico Huber |
| 2019-05-28 | soc/intel/cannonlake: Dump ME status info before notify EndOfFirmware | Bora Guvendik |
| 2019-05-22 | soc/intel/cannonlake: Dump ME f/w version and status information | Tim Wawrzynczak |
| 2019-05-20 | soc/intel/cannonlake: Make use of gpio_pm_configure() | Subrata Banik |
| 2019-05-15 | soc/intel/cannonlake: Support different SPD read type for each slot | Philip Chen |
| 2019-04-29 | soc/intel: Add GPI interrupt config register offset info | Karthikeyan Ramasubramanian |
| 2019-04-29 | soc/intel/cannonlake: Modify dq_map to provide for 6 entries | Paul Fagerburg |
| 2019-04-26 | soc/{amd,intel}/chip: Use local include for chip.h | Elyes HAOUAS |
| 2019-04-18 | soc/intel/cnl: Generate DMAR ACPI table | John Zhao |
| 2019-04-11 | soc/intel/cannonlake: Correct the GPE DWx mapping for GPIO groups | Aamir Bohra |
| 2019-04-08 | Replace remaining IS_ENABLED(CONFIG_*) with CONFIG() | Nico Huber |
| 2019-03-29 | soc/intel/cannonlake: Ignore GBE LTR | Lijian Zhao |
| 2019-03-25 | soc/intel/cannonlake: Clear PMCON status bits | Krishna Prasad Bhat |
| 2019-03-16 | soc/intel/cannonlake: Add required FSP UPD changes for CML | Subrata Banik |
| 2019-03-13 | soc/intel/cannonlake: Allow mainboard to override DRAM part number | Furquan Shaikh |
| 2019-03-08 | coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) | Julius Werner |
| 2019-03-04 | arch/io.h: Drop unnecessary include | Kyösti Mälkki |
| 2019-03-04 | soc/intel/cannonlake: Move common definitions to a header file | Rizwan Qureshi |
| 2019-02-27 | soc/intel/cannonlake: Add a config for configuring SD_VDD1_PWR_EN# | Rizwan Qureshi |
| 2019-02-27 | soc/intel/cannonlake: Add ASL functions to manipulate RX/TX buffers | Rizwan Qureshi |
| 2019-02-26 | soc/intel/cannonlake: Update GPIO definitions for Virtual GPIO | Rizwan Qureshi |
| 2019-02-22 | soc/intel/cannonlake: Add ASL function for setting pad mode | Rizwan Qureshi |
| 2019-02-21 | soc/intel/cannonlake: Add field to identify single channel memory | Shelley Chen |
| 2019-02-15 | soc/intel/cannonlake: Define VR settings | Roy Mingi Park |
| 2019-02-07 | soc/intel/cannonlake: Configure GPIOs again after FSP-S is done | Furquan Shaikh |
| 2019-01-25 | soc/intel/cannonlake: Export function to set After G3 state | Duncan Laurie |
| 2019-01-16 | soc/intel/cannonlake: Add processor power limits control support | Sumeet Pawnikar |
| 2019-01-16 | buildsystem: Promote rules.h to default include | Kyösti Mälkki |
| 2019-01-10 | soc/intel/common/block: Move tco common functions into block/smbus | Subrata Banik |
| 2019-01-09 | soc/intel/cannonlake: Enable/Disable IPU based on devicetree switch | V Sowmya |
