diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2019-02-02 13:32:49 +0530 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2019-03-16 22:48:06 +0000 |
| commit | 41483c9dff9bd68b4c67b947c4cd7175951b9723 (patch) | |
| tree | aec170fe3513fdd2156309be0eced2ed59617e7d /src/soc/intel/cannonlake/include | |
| parent | ebd8a4f90cf58cd03a95fcc01acea1c59b0cad4e (diff) | |
soc/intel/cannonlake: Add required FSP UPD changes for CML
This patch adds required FSP UPD changes for CometLake SoC.
Also this patch tries to create common parse logic for CometLake as
well as cannonlake SOC.
We parse device tree parameters for PCI devices and fill values in FSP
UPDs. We fill UPDs based on pci device config as well as SerialIoDev
config of devicetree.
For PCI devices, if PCI device is disabled from devicetree, we'll assign
disable value to FSP UPD.
In case devicetree doesn't fill this parameter or value is invalid in
SerialIoDev config, default mode will be set to PCI.
In case of valid value, we'll fill the same value into FSP UPD.
BUG=none
BRANCH=none
TEST=check if CML board boots and proper UPD values are filled.
Change-Id: Ib92b660409ab01d70358042b2ed29b8bf9cab26d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Diffstat (limited to 'src/soc/intel/cannonlake/include')
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/serialio.h | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/serialio.h b/src/soc/intel/cannonlake/include/soc/serialio.h index e152770024..6c95356d4e 100644 --- a/src/soc/intel/cannonlake/include/soc/serialio.h +++ b/src/soc/intel/cannonlake/include/soc/serialio.h @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. - * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2017-2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,12 +17,26 @@ #ifndef _SERIALIO_H_ #define _SERIALIO_H_ +#if IS_ENABLED(CONFIG_SOC_INTEL_COMETLAKE) typedef enum { + PchSerialIoNotInitialized, + PchSerialIoDisabled, + PchSerialIoPci, + PchSerialIoHidden, + PchSerialIoLegacyUart, + PchSerialIoSkipInit, + PchSerialIoMax, +} PCH_SERIAL_IO_MODE; +#else +typedef enum { + PchSerialIoNotInitialized, PchSerialIoDisabled, PchSerialIoPci, PchSerialIoAcpi, PchSerialIoHidden, + PchSerialIoMax, } PCH_SERIAL_IO_MODE; +#endif typedef enum { PchSerialIoIndexI2C0, |