| Age | Commit message (Expand) | Author |
|---|
| 2021-09-05 | soc/intel/cannonlake: Lock PAM registers in finalize | Tim Wawrzynczak |
| 2021-08-25 | soc/intel/cannonlake: Fix PCH-H IRQ constraints | Angel Pons |
| 2021-08-12 | soc/intel/cannonlake: Clean up FSP chipset lockdown configuration | Felix Singer |
| 2021-08-04 | soc/intel/cannonlake: Disable `TccOffsetClamp` if no offset is given | Nico Huber |
| 2021-08-03 | soc/intel/*: Allow configuring 8254 timer via CMOS | Sean Rhodes |
| 2021-07-01 | soc/intel: Refactor `xdci_can_enable()` function | Angel Pons |
| 2021-06-29 | soc/intel/cannonlake: Use new IRQ module | Tim Wawrzynczak |
| 2021-06-23 | soc/intel/cannonlake: Use devfn_disable() function for XDCI | Subrata Banik |
| 2021-06-16 | soc/intel/cannonlake: Make use of is_devfn_enabled() function | Subrata Banik |
| 2021-06-07 | soc/intel: Drop unused lpss functions | Furquan Shaikh |
| 2021-04-20 | soc/intel/cannonlake: Deduplicate function declaration | Felix Singer |
| 2021-04-20 | soc/intel/cannonlake: Remove unnecessary function | Felix Singer |
| 2021-02-09 | drivers/intel/fsp1_1,fsp2_0: Refactor logo display | Kyösti Mälkki |
| 2021-01-21 | soc/intel/cannonlake: Allow RP#1 usage for ClkSrc | Jeremy Soller |
| 2021-01-11 | soc/intel/cnl: Allow setting PCIe subsystem IDs after FSP-S | Jeremy Soller |
| 2020-12-17 | soc/intel/cannonlake: Change mainboard_silicon_init_params argument | Patrick Rudolph |
| 2020-11-13 | soc/intel/{skl,cnl}: replace PM ACPI timer dt option by Kconfig | Michael Niewöhner |
| 2020-10-19 | soc/intel/cannonlake: Fix memory corruptions | John Zhao |
| 2020-10-12 | soc/intel: Configure PAVP at compile-time | Benjamin Doron |
| 2020-09-21 | src/soc/intel: Drop unneeded empty lines | Elyes HAOUAS |
| 2020-09-21 | soc/intel/cnl: Use the common code to set the PchPmPwrCycDur | V Sowmya |
| 2020-09-06 | soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by default | Michael Niewöhner |
| 2020-09-04 | soc/intel/cnl: Enable HECI3 depending on devicetree | Felix Singer |
| 2020-08-23 | soc/intel/cnl: Configure FSP option PcieRpSlotImplemented | Nico Huber |
| 2020-08-07 | soc/intel/cnl: Set Heci1Disable depending on devicetree config | Felix Singer |
| 2020-07-28 | soc/intel/cannonlake: Configure SataPwrOptEnable only if SATA is enabled | Felix Singer |
| 2020-07-26 | src: Update bare access to BOOL CONFIG_ vals to CONFIG() | Martin Roth |
| 2020-07-20 | soc/intel/cannonlake: Add configs for USB 3.1 Gen2 EV settings | Jamie Chen |
| 2020-07-01 | soc/intel/cannonlake: make satahotplug user configurable via devicetree | Jonas Loeffelholz |
| 2020-06-25 | soc/intel/cannonlake: Add PchPmPwrCycDur to chip options | Sridhar Siricilla |
| 2020-06-02 | soc/intel/cannonlake: Add RP configuration settings | Christian Walter |
| 2020-05-26 | cannonlake: update processor power limits configuration | Sumeet R Pawnikar |
| 2020-05-26 | soc/intel/cannonlake: Add VrPowerDeliveryDesign to chip options | Christian Walter |
| 2020-05-11 | treewide: Remove "this file is part of" lines | Patrick Georgi |
| 2020-04-06 | soc/intel/cannonlake: Use SPDX for GPL-2.0-only files | Angel Pons |
| 2020-03-18 | soc: Remove copyright notices | Patrick Georgi |
| 2020-03-17 | soc/intel/cannonlake: Set correct serirq mode | Jeremy Soller |
| 2020-02-28 | soc/intel/cannonlake: Plumb TetonGlacierMode into dt | Edward O'Callaghan |
| 2020-02-26 | soc/intel/{cnl,icl}: Avoid static 8254 clock gating on S3 resume | Subrata Banik |
| 2019-12-19 | {drivers,soc}/intel/fsp2_0: Move chipset specific logo handling to SoC | Wim Vervoorn |
| 2019-11-27 | soc/intel/cannonlake: Disable USB2 PHY Power gating | Surendranath Gurivireddy |
| 2019-10-30 | soc/intel/cannonlake: set FSP param to enable or skip GOP | Michael Niewöhner |
| 2019-10-22 | soc/intel/cannonlake: Fix FSP UPDs settings with disabled GBE | Kane Chen |
| 2019-10-02 | soc/intel: Replace config_of_path() with config_of_soc() | Kyösti Mälkki |
| 2019-09-12 | soc/intel/cnl: Remove unnecessary FSP UPD “PchPwrOptEnable” usage | Subrata Banik |
| 2019-09-12 | soc/intel/cannonlake: Add config for sata devslp pad reset configuration | Aamir Bohra |
| 2019-09-09 | soc/intel/cannonlake: Allow coreboot to handle SPI lockdown | Subrata Banik |
| 2019-09-09 | soc/intel/cannonlake: Add ability to disable Heci1 | Bora Guvendik |
| 2019-08-26 | soc/intel/cannonlake: Add config to disable display audio codec | Aamir Bohra |
| 2019-08-20 | soc/intel/cnl: Add provision to configure SD controller write protect pin | Aamir Bohra |
| 2019-08-05 | soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOC | Aamir Bohra |
| 2019-08-02 | soc/intel/cannonlake: Disable ACPI PM timer to reduce S0ix power usage | Subrata Banik |
| 2019-07-30 | soc/intel/cannonlake: Allow coreboot to handle required chipset lockdown | Subrata Banik |
| 2019-07-29 | soc/intel/cannonlake: Correct the data type of serial_io_dev | Aamir Bohra |
| 2019-07-18 | soc/intel: Use config_of_path(SA_DEVFN_ROOT) | Kyösti Mälkki |
| 2019-07-13 | soc/intel/cnl: Sync CONFIG_LPSS_UART_FOR_CONSOLE with FSP | Nico Huber |
| 2019-07-04 | soc/intel: Replace uses of dev_find_slot() | Kyösti Mälkki |
| 2019-06-28 | soc/intel/cannonlake: fix use of legacy 8254 timer | Matt DeVillier |
| 2019-05-20 | soc/intel/cannonlake: Configure SPI CS parameters in FSP UPD. | Tim Wawrzynczak |
| 2019-05-01 | mb/google/sarien: Disable S5 wake on LAN by default | Eric Lai |
| 2019-04-26 | soc/{amd,intel}/chip: Use local include for chip.h | Elyes HAOUAS |
| 2019-04-23 | soc/intel/cannonlake: Add null reference check for Cnvi and Xdci | Aamir Bohra |
| 2019-04-22 | Revert "soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/CML" | Lijian Zhao |
| 2019-04-16 | soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/CML | Subrata Banik |
| 2019-04-08 | Replace remaining IS_ENABLED(CONFIG_*) with CONFIG() | Nico Huber |
| 2019-04-01 | soc/intel/cannonlake: Add FSP UPD to unlock GPIO pads in devicetree | Krishna Prasad Bhat |
| 2019-03-29 | soc/intel/cannonlake: Ignore GBE LTR | Lijian Zhao |
| 2019-03-27 | soc/intel/cannonlake: Configure voltage margining policies | Krzysztof Sywula |
| 2019-03-21 | soc/intel/cannonlake: Assign FSP UPDs for HPD and Data/CLK of DDI ports | Krishna Prasad Bhat |
| 2019-03-20 | soc/intel/cannonlake: Fix return values for get_param_value | Furquan Shaikh |
| 2019-03-16 | soc/intel/cannonlake: Add required FSP UPD changes for CML | Subrata Banik |
| 2019-03-08 | coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) | Julius Werner |
| 2019-02-27 | soc/intel/cannonlake: Add a config for configuring SD_VDD1_PWR_EN# | Rizwan Qureshi |
| 2019-02-22 | soc/intel/cannonlake: Add support for setting FSP-S PcieRpHotPlug from device... | Jeremy Soller |
| 2019-02-21 | src/soc/intel/cannonlake: Add PsysPmax setting | Gaggery Tsai |
| 2019-02-13 | soc/intel/cannonlake: Configure serial debug uart | Ronak Kanabar |
| 2019-01-14 | soc/intel/cannonlake: Provide interface to update TCC offset | John Su |
| 2019-01-08 | soc/intel/cannonlake: Add FSP UPD for minimum assertion width | Duncan Laurie |
| 2019-01-01 | soc/intel/cannonlake: Enable CNVi based on devicetree | Maulik V Vaghela |
| 2018-12-19 | soc/intel/cannonlake: SATA and DMI power optimize | Lijian Zhao |
| 2018-12-19 | soc/intel/cannonlake: Add Acoustic features | Lijian Zhao |
| 2018-11-17 | soc/intel/cannonlake: Add options for pcie ltr | Lijian Zhao |
| 2018-11-05 | soc/intel/cannonlake: Remove depreciated UPD selection | Lijian Zhao |
| 2018-10-09 | soc/intel/cannonlake: Disable Legacy PME for Root ports | Subrata Banik |
| 2018-10-08 | Move compiler.h to commonlib | Nico Huber |
| 2018-10-04 | soc/intel/cannonlake: Move the FSP related callbacks to separate files | Rizwan Qureshi |
