soc/intel/cannonlake: Use new IRQ module

Since GPIO IO-APIC IRQs are fixed in hardware (RO registers), this patch
allows cannonlake boards to dynamically assign PCI IRQs. This means not
relying on FSP defaults, which eliminates the problem of PCI IRQs
interfering with GPIO IRQs routed to the same IRQ, when both have
selected IO-APIC routing.

Also prodrive/hermes (intel/cannonlake) was the only user of
uart_acpi_write_irq(), therefore use the allocated IRQ instead of the
fixed IRQ number in that function to preserve behavior.

BUG=b:130217151
TEST=on dratini, grep 'IO-APIC' /proc/interrupts (compressed to fit)
   0:     11     0    0 0 IO-APIC    2-edge      timer
   1:      0   661    0 0 IO-APIC    1-edge      i8042
   8:      0     0    0 0 IO-APIC    8-edge      rtc0
   9:      0   874    0 0 IO-APIC    9-fasteoi   acpi
  14:      0     0    1 0 IO-APIC   14-fasteoi   INT34BB:00
  17:      0 10633    0 0 IO-APIC   17-fasteoi   mmc1
  19:      0     0    0 0 IO-APIC   19-fasteoi   mmc0
  22:      0     0    0 0 IO-APIC   22-fasteoi   i801_smbus
  26: 153738     0    0 0 IO-APIC   26-fasteoi   idma64.0, i2c_designwar
  27:      0     8    0 0 IO-APIC   27-fasteoi   idma64.1, i2c_designwar
  30:      0     0  227 0 IO-APIC   30-fasteoi   i2c_designware.2
  33:      0     0    0 0 IO-APIC   33-fasteoi   idma64.3
  35:  43107     0    0 0 IO-APIC   35-fasteoi   idma64.4, pxa2xx-spi.4
  36:      0     0 2039 0 IO-APIC   36-fasteoi   idma64.5, pxa2xx-spi.5
  45:      0     0 9451 0 IO-APIC   45-edge      ELAN0000:00
  85:      0     0    0 0 IO-APIC   85-fasteoi   chromeos-ec
  93:      0  7741    0 0 IO-APIC   93-edge      cr50_spi
abbreviated _PRT dump:
If (PICM)
  Package () {0x0001FFFF, 0x00, 0x00, 0x10},
  Package () {0x0001FFFF, 0x01, 0x00, 0x11},
  Package () {0x0001FFFF, 0x02, 0x00, 0x12},
  Package () {0x0002FFFF, 0x00, 0x00, 0x13},
  Package () {0x0004FFFF, 0x00, 0x00, 0x14},
  Package () {0x0005FFFF, 0x00, 0x00, 0x15},
  Package () {0x0008FFFF, 0x00, 0x00, 0x16},
  Package () {0x0012FFFF, 0x01, 0x00, 0x17},
  Package () {0x0012FFFF, 0x02, 0x00, 0x10},
  Package () {0x0012FFFF, 0x00, 0x00, 0x18},
  Package () {0x0013FFFF, 0x00, 0x00, 0x19},
  Package () {0x0014FFFF, 0x00, 0x00, 0x11}
  Package () {0x0014FFFF, 0x01, 0x00, 0x12},
  Package () {0x0014FFFF, 0x02, 0x00, 0x13},
  Package () {0x0014FFFF, 0x03, 0x00, 0x14},
  Package () {0x0015FFFF, 0x00, 0x00, 0x1A},
  Package () {0x0015FFFF, 0x01, 0x00, 0x1B},
  Package () {0x0015FFFF, 0x02, 0x00, 0x1C},
  Package () {0x0015FFFF, 0x03, 0x00, 0x1D},
  Package () {0x0016FFFF, 0x00, 0x00, 0x15},
  Package () {0x0016FFFF, 0x01, 0x00, 0x16},
  Package () {0x0016FFFF, 0x02, 0x00, 0x17},
  Package () {0x0016FFFF, 0x03, 0x00, 0x10},
  Package () {0x0017FFFF, 0x00, 0x00, 0x11},
  Package () {0x0019FFFF, 0x00, 0x00, 0x1E},
  Package () {0x0019FFFF, 0x01, 0x00, 0x1F},
  Package () {0x0019FFFF, 0x02, 0x00, 0x20},
  Package () {0x001AFFFF, 0x00, 0x00, 0x12},
  Package () {0x001CFFFF, 0x00, 0x00, 0x10},
  Package () {0x001CFFFF, 0x01, 0x00, 0x11},
  Package () {0x001CFFFF, 0x02, 0x00, 0x12},
  Package () {0x001CFFFF, 0x03, 0x00, 0x13},
  Package () {0x001DFFFF, 0x00, 0x00, 0x10},
  Package () {0x001DFFFF, 0x01, 0x00, 0x11},
  Package () {0x001DFFFF, 0x02, 0x00, 0x12},
  Package () {0x001DFFFF, 0x03, 0x00, 0x13},
  Package () {0x001EFFFF, 0x00, 0x00, 0x21},
  Package () {0x001EFFFF, 0x01, 0x00, 0x22},
  Package () {0x001EFFFF, 0x02, 0x00, 0x23},
  Package () {0x001EFFFF, 0x03, 0x00, 0x24},
  Package () {0x001FFFFF, 0x01, 0x00, 0x15},
  Package () {0x001FFFFF, 0x02, 0x00, 0x16},
  Package () {0x001FFFFF, 0x03, 0x00, 0x17},
  Package () {0x001FFFFF, 0x00, 0x00, 0x14},
Else
  Package () {0x0001FFFF, 0x00, 0x00, 0x0B},
  Package () {0x0001FFFF, 0x01, 0x00, 0x0A},
  Package () {0x0001FFFF, 0x02, 0x00, 0x0B},
  Package () {0x0002FFFF, 0x00, 0x00, 0x0B},
  Package () {0x0004FFFF, 0x00, 0x00, 0x0B},
  Package () {0x0005FFFF, 0x00, 0x00, 0x0B},
  Package () {0x0008FFFF, 0x00, 0x00, 0x0B},
  Package () {0x0012FFFF, 0x01, 0x00, 0x0B},
  Package () {0x0012FFFF, 0x02, 0x00, 0x0B},
  Package () {0x0014FFFF, 0x00, 0x00, 0x0A},
  Package () {0x0014FFFF, 0x01, 0x00, 0x0B},
  Package () {0x0014FFFF, 0x02, 0x00, 0x0B},
  Package () {0x0014FFFF, 0x03, 0x00, 0x0B},
  Package () {0x0016FFFF, 0x00, 0x00, 0x0B},
  Package () {0x0016FFFF, 0x01, 0x00, 0x0B},
  Package () {0x0016FFFF, 0x02, 0x00, 0x0B},
  Package () {0x0016FFFF, 0x03, 0x00, 0x0B},
  Package () {0x0017FFFF, 0x00, 0x00, 0x0A},
  Package () {0x001AFFFF, 0x00, 0x00, 0x0B},
  Package () {0x001CFFFF, 0x00, 0x00, 0x0B},
  Package () {0x001CFFFF, 0x01, 0x00, 0x0A},
  Package () {0x001CFFFF, 0x02, 0x00, 0x0B},
  Package () {0x001CFFFF, 0x03, 0x00, 0x0B},
  Package () {0x001DFFFF, 0x00, 0x00, 0x0B},
  Package () {0x001DFFFF, 0x01, 0x00, 0x0A},
  Package () {0x001DFFFF, 0x02, 0x00, 0x0B},
  Package () {0x001DFFFF, 0x03, 0x00, 0x0B},
  Package () {0x001FFFFF, 0x01, 0x00, 0x0B},
  Package () {0x001FFFFF, 0x02, 0x00, 0x0B},
  Package () {0x001FFFFF, 0x03, 0x00, 0x0B},
  Package () {0x001FFFFF, 0x00, 0x00, 0x0B},

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I914ac65470635f351d6311dc9b65e8e4d8d8ecfc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55968
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 208 insertions, 0 deletions

diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 89293442ba..c3989e50a6 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -7,6 +7,7 @@
 #include <device/pci.h>
 #include <fsp/api.h>
 #include <fsp/util.h>
+#include <intelblocks/irq.h>
 #include <intelblocks/lpss.h>
 #include <intelblocks/power_limit.h>
 #include <intelblocks/pmclib.h>
@@ -34,6 +35,163 @@ static const pci_devfn_t serial_io_dev[] = {
 	PCH_DEVFN_UART2
 };
 
+static const struct slot_irq_constraints irq_constraints[] = {
+	{
+		.slot = SA_DEV_SLOT_PEG,
+		.fns = {
+			FIXED_INT_PIRQ(SA_DEVFN_PEG0, PCI_INT_A, PIRQ_A),
+			FIXED_INT_PIRQ(SA_DEVFN_PEG1, PCI_INT_B, PIRQ_B),
+			FIXED_INT_PIRQ(SA_DEVFN_PEG2, PCI_INT_C, PIRQ_C),
+		},
+	},
+	{
+		.slot = SA_DEV_SLOT_IGD,
+		.fns = {
+			ANY_PIRQ(SA_DEVFN_IGD),
+		},
+	},
+	{
+		.slot = SA_DEV_SLOT_DSP,
+		.fns = {
+			ANY_PIRQ(SA_DEVFN_DSP),
+		},
+	},
+	{
+		.slot = SA_DEV_SLOT_IPU,
+		.fns = {
+			ANY_PIRQ(SA_DEVFN_IPU),
+		},
+	},
+	{
+		.slot = SA_DEV_SLOT_GNA,
+		.fns = {
+			ANY_PIRQ(SA_DEVFN_GNA),
+		},
+	},
+	{
+		.slot = PCH_DEV_SLOT_THERMAL,
+		.fns = {
+			ANY_PIRQ(PCH_DEVFN_THERMAL),
+			ANY_PIRQ(PCH_DEVFN_UFS),
+			DIRECT_IRQ(PCH_DEVFN_GSPI2),
+		},
+	},
+	{
+		.slot = PCH_DEV_SLOT_ISH,
+		.fns = {
+			DIRECT_IRQ(PCH_DEVFN_ISH),
+		},
+	},
+	{
+		.slot = PCH_DEV_SLOT_XHCI,
+		.fns = {
+			ANY_PIRQ(PCH_DEVFN_XHCI),
+			ANY_PIRQ(PCH_DEVFN_USBOTG),
+			ANY_PIRQ(PCH_DEVFN_CNViWIFI),
+			ANY_PIRQ(PCH_DEVFN_SDCARD),
+		},
+	},
+	{
+		.slot = PCH_DEV_SLOT_SIO1,
+		.fns = {
+			DIRECT_IRQ(PCH_DEVFN_I2C0),
+			DIRECT_IRQ(PCH_DEVFN_I2C1),
+			DIRECT_IRQ(PCH_DEVFN_I2C2),
+			DIRECT_IRQ(PCH_DEVFN_I2C3),
+		},
+	},
+	{
+		.slot = PCH_DEV_SLOT_CSE,
+		.fns = {
+			ANY_PIRQ(PCH_DEVFN_CSE),
+			ANY_PIRQ(PCH_DEVFN_CSE_2),
+			ANY_PIRQ(PCH_DEVFN_CSE_IDER),
+			ANY_PIRQ(PCH_DEVFN_CSE_KT),
+			ANY_PIRQ(PCH_DEVFN_CSE_3),
+			ANY_PIRQ(PCH_DEVFN_CSE_4),
+		},
+	},
+	{
+		.slot = PCH_DEV_SLOT_SATA,
+		.fns = {
+			ANY_PIRQ(PCH_DEVFN_SATA),
+		},
+	},
+	{
+		.slot = PCH_DEV_SLOT_SIO2,
+		.fns = {
+			DIRECT_IRQ(PCH_DEVFN_I2C4),
+			DIRECT_IRQ(PCH_DEVFN_I2C5),
+			DIRECT_IRQ(PCH_DEVFN_UART2),
+		},
+	},
+	{
+		.slot = PCH_DEV_SLOT_STORAGE,
+		.fns = {
+			ANY_PIRQ(PCH_DEVFN_EMMC),
+		},
+	},
+#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)
+	{
+		.slot = PCH_DEV_SLOT_PCIE_2,
+		.fns = {
+			FIXED_INT_PIRQ(PCH_DEVFN_PCIE17, PCI_INT_A, PIRQ_A),
+			FIXED_INT_PIRQ(PCH_DEVFN_PCIE18, PCI_INT_B, PIRQ_B),
+			FIXED_INT_PIRQ(PCH_DEVFN_PCIE19, PCI_INT_C, PIRQ_C),
+			FIXED_INT_PIRQ(PCH_DEVFN_PCIE20, PCI_INT_D, PIRQ_D),
+			FIXED_INT_PIRQ(PCH_DEVFN_PCIE21, PCI_INT_A, PIRQ_A),
+			FIXED_INT_PIRQ(PCH_DEVFN_PCIE22, PCI_INT_B, PIRQ_B),
+			FIXED_INT_PIRQ(PCH_DEVFN_PCIE23, PCI_INT_C, PIRQ_C),
+			FIXED_INT_PIRQ(PCH_DEVFN_PCIE24, PCI_INT_D, PIRQ_D),
+		},
+	},
+#endif
+	{
+		.slot = PCH_DEV_SLOT_PCIE,
+		.fns = {
+			FIXED_INT_PIRQ(PCH_DEVFN_PCIE1, PCI_INT_A, PIRQ_A),
+			FIXED_INT_PIRQ(PCH_DEVFN_PCIE2, PCI_INT_B, PIRQ_B),
+			FIXED_INT_PIRQ(PCH_DEVFN_PCIE3, PCI_INT_C, PIRQ_C),
+			FIXED_INT_PIRQ(PCH_DEVFN_PCIE4, PCI_INT_D, PIRQ_D),
+			FIXED_INT_PIRQ(PCH_DEVFN_PCIE5, PCI_INT_A, PIRQ_A),
+			FIXED_INT_PIRQ(PCH_DEVFN_PCIE6, PCI_INT_B, PIRQ_B),
+			FIXED_INT_PIRQ(PCH_DEVFN_PCIE7, PCI_INT_C, PIRQ_C),
+			FIXED_INT_PIRQ(PCH_DEVFN_PCIE8, PCI_INT_D, PIRQ_D),
+		},
+	},
+	{
+		.slot = PCH_DEV_SLOT_PCIE_1,
+		.fns = {
+			FIXED_INT_PIRQ(PCH_DEVFN_PCIE9,  PCI_INT_A, PIRQ_A),
+			FIXED_INT_PIRQ(PCH_DEVFN_PCIE10, PCI_INT_B, PIRQ_B),
+			FIXED_INT_PIRQ(PCH_DEVFN_PCIE11, PCI_INT_C, PIRQ_C),
+			FIXED_INT_PIRQ(PCH_DEVFN_PCIE12, PCI_INT_D, PIRQ_D),
+			FIXED_INT_PIRQ(PCH_DEVFN_PCIE13, PCI_INT_A, PIRQ_A),
+			FIXED_INT_PIRQ(PCH_DEVFN_PCIE14, PCI_INT_B, PIRQ_B),
+			FIXED_INT_PIRQ(PCH_DEVFN_PCIE15, PCI_INT_C, PIRQ_C),
+			FIXED_INT_PIRQ(PCH_DEVFN_PCIE16, PCI_INT_D, PIRQ_D),
+		},
+	},
+	{
+		.slot = PCH_DEV_SLOT_SIO3,
+		.fns = {
+			DIRECT_IRQ(PCH_DEVFN_UART0),
+			DIRECT_IRQ(PCH_DEVFN_UART1),
+			DIRECT_IRQ(PCH_DEVFN_GSPI0),
+			DIRECT_IRQ(PCH_DEVFN_GSPI1),
+		},
+	},
+	{
+		.slot = PCH_DEV_SLOT_LPC,
+		.fns = {
+			ANY_PIRQ(PCH_DEVFN_HDA),
+			ANY_PIRQ(PCH_DEVFN_SMBUS),
+			ANY_PIRQ(PCH_DEVFN_GBE),
+			FIXED_INT_ANY_PIRQ(PCH_DEVFN_TRACEHUB, PCI_INT_A)
+		},
+	},
+};
+
 /*
  * Given an enum for PCH_SERIAL_IO_MODE, 1 needs to be subtracted to get the FSP
  * UPD expected value for Serial IO since valid enum index starts from 1.
@@ -115,6 +273,46 @@ static void configure_gspi_cs(int idx, const config_t *config,
 	}
 }
 
+static const SI_PCH_DEVICE_INTERRUPT_CONFIG *pci_irq_to_fsp(size_t *out_count)
+{
+	const struct pci_irq_entry *entry = get_cached_pci_irqs();
+	SI_PCH_DEVICE_INTERRUPT_CONFIG *config;
+	size_t pch_total = 0;
+	size_t cfg_count = 0;
+
+	if (!entry)
+		return NULL;
+
+	/* Count PCH devices */
+	while (entry) {
+		if (PCI_SLOT(entry->devfn) >= MIN_PCH_SLOT)
+			++pch_total;
+		entry = entry->next;
+	}
+
+	/* Convert PCH device entries to FSP format */
+	config = calloc(pch_total, sizeof(*config));
+	entry = get_cached_pci_irqs();
+	while (entry) {
+		if (PCI_SLOT(entry->devfn) < MIN_PCH_SLOT) {
+			entry = entry->next;
+			continue;
+		}
+
+		config[cfg_count].Device = PCI_SLOT(entry->devfn);
+		config[cfg_count].Function = PCI_FUNC(entry->devfn);
+		config[cfg_count].IntX = (SI_PCH_INT_PIN)entry->pin;
+		config[cfg_count].Irq = entry->irq;
+		++cfg_count;
+
+		entry = entry->next;
+	}
+
+	*out_count = cfg_count;
+
+	return config;
+}
+
 /* UPD parameters to be initialized before SiliconInit */
 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 {
@@ -527,6 +725,16 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 
 	params->SiSsidTablePtr = (uintptr_t)ssid_table;
 	params->SiNumberOfSsidTableEntry = ARRAY_SIZE(ssid_table);
+
+	/* Assign PCI IRQs */
+	if (!assign_pci_irqs(irq_constraints, ARRAY_SIZE(irq_constraints)))
+		die("ERROR: Unable to assign PCI IRQs, and no ACPI _PRT table is defined\n");
+
+	size_t pch_count = 0;
+	const SI_PCH_DEVICE_INTERRUPT_CONFIG *upd_irqs = pci_irq_to_fsp(&pch_count);
+	params->DevIntConfigPtr = (UINT32)((uintptr_t)upd_irqs);
+	params->NumOfDevIntConfig = pch_count;
+	printk(BIOS_INFO, "IRQ: Using dynamically assigned PCI IO-APIC IRQs\n");
 }
 
 /* Mainboard GPIO Configuration */