coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2018-01-07	soc/intel/cannonlake: provide LPDDR4 memory init	Nick Vaccaro
2018-01-05	soc/intel/cannonlake: Correct PMC/GPIO routing information	Lijian Zhao
2017-12-23	soc/intel/cannonlake: Select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2	Furquan Shaikh
2017-12-22	ic2/designware: Move Intel i2c logic to shared driver	Chris Ching
2017-12-16	soc/intel/common/fast_spi: implement spi_flash_ctrlr_protect_region()	Aaron Durbin
2017-12-07	soc/intel/cannonlake: Make use of Intel common Graphics block	Subrata Banik
2017-11-13	soc/intel/cannonlake: Define default LPSS clock	Lijian Zhao
2017-11-11	soc/intel/cannonlake: Make use of Intel SPI common block	Subrata Banik
2017-11-04	soc/intel/cannonlake: Add DSP support	Lijian Zhao
2017-11-04	soc/intel/cannonlake: Install common i2c	Lijian Zhao
2017-11-01	soc/intel/cannonlake: Use SCS common code	Bora Guvendik
2017-10-27	soc/intel/cannonlake: Use common p2sb driver	Lijian Zhao
2017-10-23	soc/intel/cannonlake: Increase stack size from 4KiB to 8KiB	John Zhao
2017-10-22	soc/intel/cannonlake: Change max root port to 16	Lijian Zhao
2017-10-19	soc/intel/cannonlake: Add IGD Support and pre-OS display code	Abhay Kumar
2017-10-18	soc/intel/cannonlake: Use EBDA area to store cbmem_top address	Subrata Banik
2017-10-11	soc/intel/cannonlake: Change default UART number to 2	Lijian Zhao
2017-10-06	soc/intel/cannonlake: Enable MRC cache	Lijian Zhao
2017-10-06	soc/intel/cannonlake: reduce bootblock size	Aaron Durbin
2017-10-03	soc/intel/cannonlake: Fill the SMI usage	Lijian Zhao
2017-10-03	soc/intel/cannonlake: Add lpc pci driver	Lijian Zhao
2017-09-27	soc/intel/cannonlake: Add FSP GOP support	Abhay kumar
2017-09-13	soc/intel/cannonlake: Add common ACPI support for CNL	Lijian Zhao
2017-09-06	soc/intel/cannonlake: Add Vboot/ChromeOS support	Lijian Zhao
2017-09-01	soc/intel/cannonlake: Define Max PCIE Root Ports	Pratik Prajapati
2017-09-01	soc/intel/cannonlake: add gpio files to make	Nick Vaccaro
2017-09-01	soc/intel/canonlake: Enable LPSS UART in 32bit PCI mode	Lijian Zhao
2017-08-30	soc/intel/{cannonlake,skylake}: Add active default value for UART_FOR_CONSOLE	Subrata Banik
2017-08-25	soc/intel/cannonlake: Init UPD params based on config	Pratik Prajapati
2017-08-24	soc/intel/cannonlake: Add cpu.c and MP init support	Pratik Prajapati
2017-08-21	soc/intel/cannonlake: Enable common PMC code for CNL	Lijian Zhao
2017-08-21	soc/intel/cannonlake: Add Kconfig option to select UART index	Subrata Banik
2017-08-17	soc/intel/cannonlake: Add SPI flash controller driver	Lijian Zhao
2017-08-15	soc/intel/cannonlake: Add postcar stage support	Lijian Zhao
2017-08-11	soc/cannonlake: Enable SMM code for Cannon Lake	Brandon Breitenstein
2017-08-03	soc/intel/cannonlake: Sort Kconfig for Cannonlake	Lijian Zhao
2017-07-21	Revert "soc/intel/cannonlake: Add postcar stage support"	Martin Roth
2017-07-21	soc/intel/cannonlake: Add postcar stage support	Lijian Zhao
2017-07-20	soc/intel/cannonlake: Make ramstage relocatable	Lijian Zhao
2017-07-19	soc/intel/cannonlake: Add microcode support	Lijian Zhao
2017-07-18	soc/intel/cannonlake: Use common GPIO driver	Andrey Petrov
2017-07-13	soc/intel/cannonlake: Add early CPU initialization	Andrey Petrov
2017-06-29	soc/intel/cannonlake: Add initial dummy directory	Lijian Zhao