diff options
| author | Andrey Petrov <andrey.petrov@intel.com> | 2017-06-05 13:22:24 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-07-13 19:28:27 +0000 |
| commit | 3e2e0508c2f41242355dfbfe42b9e34adcb1a92a (patch) | |
| tree | 2b271acdb1a7f9afe3ff4a49cdd226c29914a320 /src/soc/intel/cannonlake/Kconfig | |
| parent | 5b8987ae46512b5550d15fafd54b270ec913422d (diff) | |
soc/intel/cannonlake: Add early CPU initialization
Add basic CPU initialization for bootblock, as well as relevant headers.
Change-Id: I318b7ea0f3aa5b5d28bf70784ccd20f2fe28cd86
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/20066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/cannonlake/Kconfig')
| -rw-r--r-- | src/soc/intel/cannonlake/Kconfig | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 5da39b961f..3012c6165b 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -11,6 +11,7 @@ config CPU_SPECIFIC_OPTIONS select ARCH_VERSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 + select SOC_INTEL_COMMON_BLOCK_TIMER select HAVE_MONOTONIC_TIMER select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER @@ -25,6 +26,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_CAR + select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_BLOCK_LPSS select SOC_INTEL_COMMON_BLOCK_UART @@ -64,4 +66,8 @@ config PCR_BASE_ADDRESS help This option allows you to select MMIO Base Address of sideband bus. +config CPU_BCLK_MHZ + int + default 100 + endif |