From 3e2e0508c2f41242355dfbfe42b9e34adcb1a92a Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Mon, 5 Jun 2017 13:22:24 -0700 Subject: soc/intel/cannonlake: Add early CPU initialization Add basic CPU initialization for bootblock, as well as relevant headers. Change-Id: I318b7ea0f3aa5b5d28bf70784ccd20f2fe28cd86 Signed-off-by: Andrey Petrov Reviewed-on: https://review.coreboot.org/20066 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/cannonlake/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/soc/intel/cannonlake/Kconfig') diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 5da39b961f..3012c6165b 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -11,6 +11,7 @@ config CPU_SPECIFIC_OPTIONS select ARCH_VERSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 + select SOC_INTEL_COMMON_BLOCK_TIMER select HAVE_MONOTONIC_TIMER select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER @@ -25,6 +26,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_CAR + select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_BLOCK_LPSS select SOC_INTEL_COMMON_BLOCK_UART @@ -64,4 +66,8 @@ config PCR_BASE_ADDRESS help This option allows you to select MMIO Base Address of sideband bus. +config CPU_BCLK_MHZ + int + default 100 + endif -- cgit v1.2.3