Age | Commit message (Expand) | Author |
2015-06-04 | devicetree: Change scan_bus() prototype in device ops | Kyösti Mälkki |
2015-06-04 | devicetree: Discriminate device ops scan_bus() | Kyösti Mälkki |
2015-06-02 | assets: abstract away the firmware assets used for booting | Aaron Durbin |
2015-06-02 | cbfs: new API and better program loading | Aaron Durbin |
2015-05-29 | chromeos: always enable timestamps | Stefan Reinauer |
2015-05-28 | smm: Merge configs SMM_MODULES and SMM_TSEG | Vladimir Serbinenko |
2015-05-27 | Move TPM code out of chromeos | Vladimir Serbinenko |
2015-05-26 | acpi: Remove monolithic ACPI | Vladimir Serbinenko |
2015-05-23 | baytrail: Switch to per-device ACPI | Vladimir Serbinenko |
2015-05-21 | Remove address from GPLv2 headers | Patrick Georgi |
2015-05-13 | baytrail: broadwell: correct refcode loading | Aaron Durbin |
2015-05-05 | 3rdparty: move to 3rdparty/blobs | Patrick Georgi |
2015-05-05 | 3rdparty: Move to blobs | Patrick Georgi |
2015-05-01 | intel: Correct MMIO related ACPI table settings | Dave Frodin |
2015-04-30 | kbuild: Don't require intel/common changes for every soc | Stefan Reinauer |
2015-04-29 | kbuild: automatically include SOCs | Stefan Reinauer |
2015-04-22 | coreboot: common stage cache | Aaron Durbin |
2015-04-15 | soc/baytrail: Use microcode from the blobs repository | Marc Jones |
2015-04-10 | baytrail: correct NC pin to GPO pin according to BYT platform design guide | Kane Chen |
2015-04-10 | baytrail: add code for supporting 2x ddr refresh rate | Kane Chen |
2015-04-10 | baytrail: fix the coding error on PCIe L1 exit latency | Kevin L Lee |
2015-04-10 | Baytrail: Prior to PCI scan, wait for LCTL to be active in 50 ms | Kevin Hsieh |
2015-04-10 | baytrail: Switch from ACPI mode to PCI mode for legacy support | Marc Jones |
2015-04-07 | baytrail: Change all SoC headers to <soc/headername.h> system | Julius Werner |
2015-04-06 | baytrail: Fix hdmi audio choppy issue | Kein Yuan |
2015-04-06 | baytrail: reinitialize spi controller in SMM finalization | Aaron Durbin |
2015-04-04 | Baytrail: Fix no_dev_behind_port not executed for RP1/2/3. | Kenji Chen |
2015-04-03 | rmodule: use struct prog while loading rmodules | Aaron Durbin |
2015-04-02 | baytrail: Change USB3 PLL VCO and iCLK PLL current on BYT-M/D CPU | Kein Yuan |
2015-04-02 | Baytrail: Change PCIe root disable algorithm | Kenji Chen |
2015-04-02 | Baytrail: add _PRT to each PCIe root port device | Ted Kuo |
2015-04-01 | cbfs: correct types used for accessing files | Aaron Durbin |
2015-03-30 | baytrail: fix HAVE_REFCODE_BLOB build errors | Aaron Durbin |
2015-03-30 | Update hex values to CBFS binary name types in Makefiles | Martin Roth |
2015-03-18 | bootstate: use structure pointers for scheduling callbacks | Aaron Durbin |
2015-03-10 | ACPI: Get S3 resume state from romstage_handoff | Kyösti Mälkki |
2015-03-09 | coreboot: fix munged license text | Aaron Durbin |
2015-02-25 | soc/intel/baytrail/Kconfig: Remove explicit `HAVE_MONOTONIC_TIMER` | Paul Menzel |
2015-02-16 | acpi: Generate valid ACPI processor objects | Timothy Pearson |
2015-02-15 | x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer | Kevin Paul Herbert |
2015-01-27 | CBMEM: Always use DYNAMIC_CBMEM | Kyösti Mälkki |
2015-01-27 | CBMEM: Do not use get_top_of_ram() with DYNAMIC_CBMEM | Kyösti Mälkki |
2015-01-27 | vboot2: add verstage | Stefan Reinauer |
2015-01-16 | baytrail: there is a chance that USBPHY_COMPBG is set to 0 | Kane Chen |
2015-01-16 | baytrail: use the setting in devicetree.cb to config USBPHY_COMPBG | Kane Chen |
2015-01-14 | baytrail broadwell: Use timestamps internal stash | Kyösti Mälkki |
2015-01-05 | timestamps: Switch from tsc_t to uint64_t | Stefan Reinauer |
2014-12-31 | baytrail: add more gpio init macros | Kane Chen |
2014-12-30 | baytrail: Add defines and functions for GPNCORE | Kein Yuan |
2014-12-28 | intel baytrail broadwell: Include microcode updates | Kyösti Mälkki |
2014-12-19 | baytrail SOCs: Add missing comma in gpio.h | Martin Roth |
2014-12-17 | baytrail: initialize backlight PWM frequency | Aaron Durbin |
2014-12-17 | x86: Initialize SPI controller explicitly during PCH init | David Hendricks |
2014-12-09 | spi: Eliminate the spi_cs_activate and spi_cs_deactivate functions. | Gabe Black |
2014-12-09 | spi: Remove the spi_set_speed and spi_cs_is_valid functions. | Gabe Black |
2014-12-08 | intel/baytrail: Spelling fixes | Martin Roth |
2014-12-02 | Replace hlt with halt() | Patrick Georgi |
2014-11-30 | Replace hlt() loops with halt() | Patrick Georgi |
2014-11-25 | intel: Remove IRQ1 from possible PIRQ assignemnt. | Vladimir Serbinenko |
2014-11-18 | baytrail: fix range check | Patrick Georgi |
2014-11-13 | intel: use crosscompiler readelf, instead of global | Patrick Georgi |
2014-11-09 | src: Too many terminators ';;' at end of stmts, stop Skynet | Edward O'Callaghan |
2014-11-01 | {cpu,soc}: Use DEVICE_NOOP macro over dummy symbol | Edward O'Callaghan |
2014-10-28 | baytrail: Remove unused devicetree fields | Shawn Nematbakhsh |
2014-10-28 | baytrail: gfx: Don't configure hotplug + backlight registers | Shawn Nematbakhsh |
2014-10-28 | Baytrail/dptf: Always return 0 in TCPU._PPC | Kein Yuan |
2014-10-28 | baytrail: handle MRC being an ELF file | Aaron Durbin |
2014-10-28 | baytrail: Configure MSR for 2-core and 4-core P-state configutation | Duncan Laurie |
2014-10-28 | baytrail: move cache-as-ram base address to 0xfe000000 | Aaron Durbin |
2014-10-28 | baytrail: romstage: Add function to check SW WP status for vboot | Shawn Nematbakhsh |
2014-10-22 | reg_script: default to n for ARCH_X86 | Isaac Christensen |
2014-10-22 | cmos: Rename the CMOS related functions. | Gabe Black |
2014-10-22 | baytrail: Move HDA verb table to Intel SOC common directory | Duncan Laurie |
2014-10-22 | baytrail: Move MRC cache code to a common directory | Duncan Laurie |
2014-10-22 | baytrail/rambi: S3 support and other updates | Kein Yuan |
2014-10-19 | x86 romstage: Move stack just below RAMTOP | Kyösti Mälkki |
2014-10-19 | haswell baytrail: Enable RELOCATABLE_RAMSTAGE | Kyösti Mälkki |
2014-10-14 | baytrail: Add padding to the end of device_nvs to match ACPI | Scott Radcliffe |
2014-10-01 | baytrail: update C0 microcode | Shawn Nematbakhsh |
2014-09-24 | baytrail: add 80c microcode for C0 parts | Aaron Durbin |
2014-09-19 | baytrail/rambi: spi, charger, and audio updates | Aaron Durbin |
2014-09-18 | rambi/baytrail: ACPI, GPIO, audio, misc updates | Shawn Nematbakhsh |
2014-08-28 | soc/intel/baytrail/Kconfig: Remove empty line at top file | Paul Menzel |
2014-08-15 | Move baytrail-specific config to baytrail. | Vladimir Serbinenko |
2014-07-23 | src/.../Kconfig: various small fixes to texts | Daniele Forsi |
2014-07-17 | soc,ASL: Trivial - drop trailing blank lines at EOF | Edward O'Callaghan |
2014-07-14 | SPI: Split writes using spi_crop_chunk() | Kyösti Mälkki |
2014-07-08 | soc: Trivial - drop trailing blank lines at EOF | Edward O'Callaghan |
2014-07-05 | spi: Change spi_xfer to work in units of bytes instead of bits. | Gabe Black |
2014-07-05 | spi: Remove unused parameters from spi_flash_probe and setup_spi_slave. | Gabe Black |
2014-06-21 | intel boards: Use acpi_is_wakeup_s3() | Kyösti Mälkki |
2014-06-18 | ACPI: Remove CBMEM TOC from GNVS | Kyösti Mälkki |
2014-05-17 | build: separate CPPFLAGS from CFLAGS | Patrick Georgi |
2014-05-17 | build: CPPFLAGS is more common than INCLUDES | Patrick Georgi |
2014-05-15 | baytrail: Add SOC thermal settings | Duncan Laurie |
2014-05-15 | baytrail: Enable PCIe common clock and ASPM | Duncan Laurie |
2014-05-15 | baytrail: enable graphics turbo | Aaron Durbin |
2014-05-15 | baytrail: use CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED | Aaron Durbin |
2014-05-15 | baytrail: Add ACPI Device for XHCI | Duncan Laurie |
2014-05-15 | baytrail: nvm: use proper types for checking erase | Aaron Durbin |