diff options
| author | Scott Radcliffe <sradcliffe@microind.com> | 2014-10-10 16:15:01 -0400 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2014-10-14 18:59:07 +0200 |
| commit | bf9d6a856788f7bae7c3732b1761adb99ac3914f (patch) | |
| tree | 512ce42c004e3b6316e55a3c20b2c3dcbd5b1d69 /src/soc/intel/baytrail | |
| parent | 375e6ce4aeee449c34a6d3efb6374c5684f7b32f (diff) | |
baytrail: Add padding to the end of device_nvs to match ACPI
ACPI globalnvs.asl expects the gnvs memory area size to be 0x2000.
Padding has been added to device_nvs struct to reserve the full
0x2000 bytes for gnvs usage.
No known issues are caused by having the GNVS area shorter than
what ACPI thinks. Since there's nothing defined in this area,
O/S shouldn't try to access it. Only problem might be if O/S
notices the SSDT is located within the GNVS defined area.
I verified that the next table written to memory (SSDT) is 0x2000
past GNVS start using a custom-designed Baytrail-I motherboard
based on the Intel Bayley Bay CRB.
Change-Id: I9792954c7a3403eba6f37d7e53ea4a9ed3a2e4ac
Signed-off-by: Scott Radcliffe <sradcliffe@microind.com>
Reviewed-on: http://review.coreboot.org/7039
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/soc/intel/baytrail')
| -rw-r--r-- | src/soc/intel/baytrail/baytrail/device_nvs.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/baytrail/device_nvs.h b/src/soc/intel/baytrail/baytrail/device_nvs.h index f8f831b735..1ed897f8e5 100644 --- a/src/soc/intel/baytrail/baytrail/device_nvs.h +++ b/src/soc/intel/baytrail/baytrail/device_nvs.h @@ -62,6 +62,7 @@ typedef struct { /* Extra */ u32 lpe_fw; /* LPE Firmware */ + u8 rsvd1[3930]; /* Add padding so sizeof(device_nvs_t) == 0x1000 */ } __attribute__((packed)) device_nvs_t; #endif |