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path: root/src/soc/intel/apollolake
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2023-01-01apollolake/include/soc/meminit.h: Add missing stdboolElyes Haouas
stdbool is added through types.h file. Change-Id: I317faf322a7e73b706724802d99815ab50e655e2 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-27tree/acpi: Replace constant "Zero" with actual numberFelix Singer
Change-Id: I5a3e3506415f424bf0fdd48fc449520a76622af5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71525 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27{acpi,arch,soc}/acpi: Replace constant "One" with actual numberFelix Singer
Change-Id: I3dfd7dd1de3bd27c35c195bd43c4a5b8c5a2dc53 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71522 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23soc/intel: Drop SoC specific DPTF implementationSubrata Banik
This patch drops the SoC specific implementation as DPTF driver can now fillin those platform specific data using SoC specific macros. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: If65976f15374ba2410b537b1646ce466ba02969b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-22soc/intel/apollolake/acpi: Remove STOM from ACPISean Rhodes
This should only contain resources that the PCI domain uses. Stolen memory prevents the PCI domain from allocating anything where it is. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I1562396f0b747a81bbc584314956809bd3865ff9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66267 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22soc/intel/apollolake/acpi: Improve comments and unify code word spellingSean Rhodes
ACPI: Improve comments and unify code word spelling Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I1efbe930d0b8daec7c7bd2c1d84a4a3a5cad2ffb Reviewed-on: https://review.coreboot.org/c/coreboot/+/66245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22soc/intel/apollolake/acpi: Tidy the Legacy video RAMSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie6572638c6bbe910745de55afa44458fb6b8db9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66240 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22soc/intel/apollolake/acpi: Tidy the PCI Memory RegionSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I8997f9c111142a908b60675023d1a7dd86d3632a Reviewed-on: https://review.coreboot.org/c/coreboot/+/66238 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22soc/intel/apollolake/acpi: Add bits of TOLUD registerSean Rhodes
The values in this patch were found in the following datasheets: * 334819 (APL) * 336561 (GLK) Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9a4a05f9c764eecaac3d473ba612dca6cc81518f Reviewed-on: https://review.coreboot.org/c/coreboot/+/66234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-12-22soc/intel/apollolake/acpi: Remove TOUUD as it is not usedSean Rhodes
Remove Top of Upper Usable DRAM Low from MCHC as it isn't needed. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ifdd8c9ba61c5b1c6b154369413470e431ce8f5b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66231 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22soc/intel/apollolake/acpi: Add PDRC for PCIX and ACPI to allow use of MMCONFSean Rhodes
The current implementation of the MCRS had several issues with BARs and MMCONF not being available: [ 0.156231] pci 0000:00:02.0: BAR 2: assigned to efifb [ 0.165302] pci 0000:00:18.2: can't claim BAR 0 [mem 0xddffc000-0xddffcfff 64bit]: no compatible bridge window [ 0.192896] pci 0000:00:18.2: BAR 0: assigned [mem 0x280000000-0x280000fff 64bit] ... [ 0.138300] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000) [ 0.138300] PCI: not using MMCONFIG [ 0.148014] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000) [ 0.149674] [Firmware Info]: PCI: MMCONFIG at [mem 0xe0000000-0xefffffff] not reserved in ACPI motherboard resources [ 0.149679] PCI: not using MMCONFIG [ 0.155052] acpi PNP0A08:00: fail to add MMCONFIG information, can't access extended PCI configuration space under this bridge. This new MCRS, tested on the Star Lite Mk IV, resolves these issues: [ 0.158786] pci 0000:00:02.0: BAR 2: assigned to efifb [ 0.197391] pci 0000:00:1f.1: BAR 0: assigned [mem 0x280000000-0x2800000ff 64bit] ... [ 0.138460] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000) [ 0.138460] PCI: not using MMCONFIG [ 0.150889] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000) [ 0.152548] PCI: MMCONFIG at [mem 0xe0000000-0xefffffff] reserved in ACPI motherboard resources Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib6fc58efc9aadb5828251e0260622dac7ea3ef2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66244 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-12-22soc/intel: Set `use_eisa_hids` based on `DPTF_USE_EISA_HID` configSubrata Banik
This patch avoids hardcoding to the `use_eisa_hids` variable instead relying on the SoC config to choose if the SoC platform supports EISA HID. If any SoC platform has the support then the `use_eisa_hids` variable would be set to `true` based on the selection of `DPTF_USE_EISA_HID` config. Note: Prior to Tiger Lake, all DPTF devices used 7-character EISA IDs. If selected, the 7-character _HIDs will be emitted, otherwise, it will use the "new" style, which are regular 8-character _HIDs. Ideally, the platform prior to Tiger Lake would set `use_eisa_hids` to `true` and platform posts that would set `use_eisa_hids` to `false`. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I869bebc8e17c1e65979ca3431308d69771a34fa3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71110 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-22soc/intel/{apl,cnl,jsl}: Enable EISA HID support for DPTFSubrata Banik
This patch selects `HAVE_DPTF_EISA_HID` config for APL, CNL and JSL platform. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ice01c5720ba7f15861899d89981225cb76f9fcd5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71109 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-22soc/intel/apollolake: Move DPTF ACPI Device IDs into header fileSubrata Banik
This patch moves DPTF ACPI Device IDs into the header file (soc/dptf.h) so that upcoming patches in this patch train can achieve more common code. TEST=Able to build and boot Google/Reef. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0ce956351afc06871c465b67f51cba8786ce52db Reviewed-on: https://review.coreboot.org/c/coreboot/+/71104 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-22drivers/intel/dptf: Add `soc_` prefix for `get_dptf_platform_info()`Subrata Banik
This patch makes the SoC specific callback code more readable by adding `soc_` prefix into the `get_dptf_platform_info()`. In nutshell this patch renames `get_dptf_platform_info()` to `soc_get_dptf_platform_info()`. TEST=Able to build Google/Rex without any compilation issue. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I27d6a146d5928e1742f82f85f51ad42656f46344 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-12-16soc/intel/apollolake/acpi/northbridge.asl: Fix commentElyes Haouas
This fixes the following error: In file included from src/mainboard/siemens/mc_apl1/dsdt.asl:21: src/soc/intel/apollolake/acpi/northbridge.asl:15:12: warning: '/*' within block comment [-Wcomment] PXEN, 1, /* Enable */ ^ Change-Id: I1173eed69847f4c3b307ce96d76fb7185dc2f85c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70767 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-12-13soc/intel/apollolake/pmutil.c: Use {read,wrire}32p()Elyes Haouas
Change-Id: Iab3215487d0a19e0791a78f953a8545dfae3d2dc Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-12soc/apollolake: Add DPTF HIDsSean Rhodes
Add the HIDs that Windows uses for the DPTF driver. Change-Id: Ic0cb4a45b5ebaf777a09bed1e5836e8afd873657 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66013 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-07soc/intel: Set IO APIC DMAR entry based on hwArthur Heymans
This avoids the need to hardcode the IOAPIC ID. Change-Id: I0965b511e71c58f1c31433bc54595a5fabb1c206 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70268 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-11-28sb,soc/intel: Address TCO SECOND_TO_STS name collisionKyösti Mälkki
Later soc/intel/common/smbus addresses TCO2_STS as a separate 16-bit register, while baytrail and braswell assumes 32-bit wide TCO1_STS to extend as TCO2_STS. In src/soc/intel/denverton_ns: #define TCO2_STS_SECOND_TO 0x02 In soc/intel/baytrail,braswell: #define SECOND_TO_STS (1 << 17) Elsewehere #define SECOND_TO_STS (1 << 1) It's expected that we remove the first (1 << 17) case and only access TCO2_STS as a separate 16-bit register. For now, use unique names to avoid confusion. Change-Id: I07cc46a9d600b2bf2f23588b26891268e9ce4de0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-26src/soc/intel: Remove unnecessary space after castsElyes Haouas
Change-Id: I098104f32dd7c66d7bb79588ef315a242c3889ba Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-17soc/intel: Add node_num to dimm_info struct + adjust dimm_info_fillDavid Milosevic
The dimm_info structure (defined in src/include/memory_info.h) currently does not hold information about the DIMM's node/controller ID. This patch extends the dimm_info structure by adding a new field for the node ID, called node_num. Also, adapt the dimm_info_fill() function accordingly to populate the newly-added field. Background: These changes are necessary for the Atlas mainboard, where we are currently experiencing issues with the DIMMs device/bank locator. Our 2 DIMMs share the same CHANNEL and DIMM ID but have a distinct NODE ID. By looking at the smbios table we see Channel-0-DIMM-0 for both DIMMs. Thus, we need their NODE IDs in order to distinguish them. This patch was tested by building and booting for the Alderlake-P RVP board, which has the same DIMM slot configuration as the Prodrive Atlas mainboard. Signed-off-by: David Milosevic <David.Milosevic@9elements.com> Change-Id: I6ffa5bdff0ba0e3c4a4a51f2419291fd1278cd68 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68525 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-04soc/intel: Include <cpu/cpu.h> instead of <arch/cpu.h>Elyes Haouas
Also sort includes. Change-Id: I7da9c672ee230dfaebd943247639b78d675957e4 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-10-31soc: Add SPDX license headers to MakefilesMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic875708697f07b6dae09d27dbd67eb8b960749f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-10-22payloads/edk2: Disable the CPU Timer Lib unless supportedSean Rhodes
For recent X86 CPUs, the 0x15 CPUID instruction will return Time Stamp Counter Frequence. For CPUs that do not support this instruction, EDK2 must include a different library which is the reason why this must be configured at build time. If this is enabled, and the CPU doesn't support 0x15, it will fail to boot. If is not enabled, and the CPU does support 0x15, it will still boot but without support for the leaf. Consequently, disabled it by default. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4f0f43ce50c4f6f7eb03063fff34d015468f6daa Reviewed-on: https://review.coreboot.org/c/coreboot/+/65950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-21soc/intel/apollolake: Skip SMI lockdown on ApollolakeMatt DeVillier
Commit d9ef02ce (soc/intel/apollolake: Lock down Global SMI) breaks SMM/SMI on Apollolake (but not Geminilake), so guard it accordingly. TEST=build/boot google/reef, verify SMM/SMI/SMMSTORE functional. Change-Id: I00cbe046b61e6c342f7961670478d0ca8d365c2e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-15soc/intel/apollolake: Lock down Global SMISean Rhodes
Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9377c3b65aa342f754c303148b0b8d826d05bb94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67662 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-15soc/intel/apollolake: Configure FSP UPDs to allow coreboot to lockdownSean Rhodes
Configure FSP S UPDs to allow coreboot to handle the lockdown. The main change here is setting `Write Protection Support` to 0, as the default is Enabled, which shouldn't allow writes (even though it seems to). The UPDs are identical on APL and GLK, but all ones configured in this patch have been there since their initial releases. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I1f6e5344cab2af7aa6001b9ec0f07b043a9caa8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/67754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-12treewide: Use 'fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk'Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I7ddb4ea792b9a2153b7c77d2978d9e1c4544535d Reviewed-on: https://review.coreboot.org/c/coreboot/+/68275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-07soc/intel/apollolake: Add UFS InterruptSean Rhodes
According to Intel document number 336561, GLK has UFS (0x1d), so add the PCI interrupt. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I68bac590bd1a9a0b8213440e882c8f431f06c95f Reviewed-on: https://review.coreboot.org/c/coreboot/+/67680 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-07soc/intel/apollolake: Remove SD Card interrupt for GLKSean Rhodes
According to Intel document number 336561, G, SD Card (0x1b) does not exist on GLK, so remove it. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I6921fc3db430c76ec54cf832ce51c627a507385c Reviewed-on: https://review.coreboot.org/c/coreboot/+/67679 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-06soc/intel/apollolake/acpi: Add PCIEXBAR to MCHCSean Rhodes
The values in this patch were found in the following datasheets: * 334819 (APL) * 336561 (GLK) Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I14c5933b9022703c8951da7c6a26eb703258ec37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-27acpi/acpi_pm.c: refactor acpi_pm_state_for_* functionsFabio Aiuto
Use just one function to get the chipset powerstate and add an argument to specify the powerstate claimer {RTC,ELOG,WAKE} and adjust the failure log accordingly. TEST: compile tested and qemu emulation successfully run Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com> Change-Id: I8addc0b05f9e360afc52091c4bb731341d7213cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/67618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-22soc/intel/common/pch: Add a block specific to Apollo LakeSean Rhodes
Add SOC_INTEL_COMMON_PCH_CLIENT which is specific to Apollo Lake. This is used to select the options that Apollo Lake requires, without the ones specific to a PCH as Apollo Lake doesn't have a PCH. This change also enables SOC_INTEL_COMMON_PCH_LOCKDOWN for Apollo Lake. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I084a05f904a19f3b7e9a071636659670aa45bf3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-09-20Revert "soc/intel/apollolake: Configure FSP UPDs to allow coreboot to lockdown"Tim Wawrzynczak
This reverts commit 7ef5376123d4d0ebb811795fcee1de7066f65a0f. Reason for revert: It was merged before its dependencies so now master is broken. Change-Id: Ia270efaed4f5c9d0c7b9761ae22dec55f57f74cf Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67285 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19soc/intel/apollolake: LZ4 Compress FSP-MArthur Heymans
FSP-M is not run XIP so it can be compressed. This more than halves the binary size. 364544 bytes -> 168616 bytes. On the up/squared this also results in a 83ms speedup. TESTED: up/squared boots. Change-Id: Ic76b51f0f3007b59ccb9f76b6a57bb9265dab833 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-09-19soc/intel/apollolake: Add bits of GEN_PMCON2 registerSean Rhodes
The values in this patch were found in the following datasheets: * 334819 (APL) * 336561 (GLK) Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie7d40395d754b2abdf9079d6ee5e8ab8c536d449 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67661 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19soc/intel/apollolake: Configure FSP UPDs to allow coreboot to lockdownSean Rhodes
Configure FSP S UPDs to allow coreboot to handle the lockdown. The main change here is setting `Write Protection Support` to 0, as the default is Enabled, which shouldn't allow writes (even though it seems to). The UPDs are identical on APL and GLK, but all ones configured in this patch have been there since their initial releases. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I35185b498315511f3236758caebfe2f9c28fd04a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65039 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-14timer: Change timer util functions to 64-bitRob Barnes
Since mono_time is now 64-bit, the utility functions interfacing with mono_time should also be 64-bit so precision isn't lost. Fixed build errors related to printing the now int64_t result of stopwatch_duration_[m|u]secs in various places. BUG=b:237082996 BRANCH=All TEST=Boot dewatt Change-Id: I169588f5e14285557f2d03270f58f4c07c0154d5 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-09-01vendorcode/intel/fsp2/glk: Add the FSP headers for version 2.2.3.1Sean Rhodes
Add the headers for 2.2.3.1, which includes the following changes over 2.2.0.0: • [Implemented]GLK: XHCLKGTEN Register setting causes S0ix entry failure in less than 5 cycles when a USB2 Ethernet Dongle is connected. Refer GLK BIOS Spec Volume1 CDI# 571118 under chapter 7.20.6 for new Register settings. • [Implemented] [GLK/GLK-R] DDR4 16Gb SDP Memory support for Gemini Lake/Gemini Lake – R • [Update] MRC new version update to 1.38. • [Fixed][GLK-R][WLAN] Removed the DSW function - Wake on LAN from S4 issue with latest Wifi driver. [Update] MRC new version update to 1.39. Included fix for MinRefRate2xEnable and support for Rowhammer mitigation. • [Fixed] Disable Dynamic DiffAmp and set CTLE from 7 to 5. This change specific to DDR4 memory configuration. • GLK Klocwork Fix • [Update] MRC new version update to 1.40. Added in a separate directory as the default. The 2.2.0.0 headers were left and will be used for Google boards, as some offsets have moved. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I09498368b116c2add816eeada2fa4d0dba6e5765 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-08-17soc/intel/apollolake: Add the remaining CSE Firmware Status RegistersSean Rhodes
Add the Shadow Registers from 2 through 5 and print information from them accordingly. All values were taken from Intel document number 571993. Tested on the StarLite Mk III and the correct values are shown: [DEBUG] CSE: IBB Verification Result: PASS [DEBUG] CSE: IBB Verification Done : YES [DEBUG] CSE: Actual IBB Size : 88 [DEBUG] CSE: Verified Boot Valid : FAIL [DEBUG] CSE: Verified Boot Test : NO [DEBUG] CSE: FPF status : FUSED Please note, the values shown are in an error state. This replaces the Fuse check that is done via Heci, as this will only work whilst the CSE is in a normal state. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I8a9e7b329010fae1a2ed9c3fefc9765e617cdfe4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-17soc/intel/apollolake: Enable DPTF & SMBus as it is a required deviceSean Rhodes
coreboot is unable to disable certain devices, whilst many are hidden DPTF and SMBus are not. Set this to enabled chipset so that it is enabled by default. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I85d74179b6fe3c6126566422f82f7b806f80d0c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-22soc/apollolake: Don't select VBNV_CMOS if VBNV_FLASH is enabledSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If8af4657508f00feff8525b0135c7f73c1959965 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-20treewide: Remove unused <cpu/x86/msr.h>Elyes Haouas
Change-Id: I187c2482dd82c6c6d1fe1cbda71710ae1a2f54ad Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-20soc/apollolake: Add CSE Firmware Status RegistersSean Rhodes
Add the CSE, General Status and Miscellaneous registers and print information from them accordingly. All values were taken from Intel document number 571993. Tested on the StarLite Mk III and the correct values are shown: [DEBUG] CSE: Working State : 2 [DEBUG] CSE: Manufacturing Mode : NO [DEBUG] CSE: Operation State : 1 [DEBUG] CSE: FW Init Complete : NO [DEBUG] CSE: Error Code : 3 [DEBUG] CSE: Operation Mode : 0 [DEBUG] CSE: FPF status : unknown Please note, the values shown are in an error state. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I1a5548132dadbb188a33a7ae30a0a1fa144d130f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-19soc/intel/apollolake: Call heci_init in romstageSean Rhodes
Call heci_init to initialise all Heci devices and bring them to d0. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Id2865b649331846fc119da7c4be56cc1fed56b8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/64860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-08soc/intel/apollolake/meminit.c: Remove unuseful commentElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ia81b4397c92f100abad9b1e974bbebfe49008439 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-08soc/intel/apollolake: Fix incorrect GPE numberReka Norman
BUG=None TEST=None Signed-off-by: Reka Norman <rekanorman@chromium.org> Change-Id: I2eb6e94e5d87bb19b11e27461e2b5bdaee9d59bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65691 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-28soc/intel/apollolake: Add chipset devicetreeSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ic2b9a22bc6c32030f960d59b2874be5459c3ba28 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-23soc/intel/apollolake: Enable SATA Power OptimisationSean Rhodes
Enable PwrOptEnable FSP S UPD and hook it to the inverted value of SataPwrOptimizeDisable to allow it to be disabled from the devicetree. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I056fd7b16dadb213b3326523b0c7943ce35b8dc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-06-22device/resource: Add _kb postfix for resource allocatorsKyösti Mälkki
There is a lot of going back-and-forth with the KiB arguments, start the work to migrate away from this. Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-20soc/intel/apollolake: Hook Up SataPortEnable to devicetreeSean Rhodes
Hook Up SataPortsEnable to the devicetree. As the default value is 0, set both [0] and [1] in all mainboards so they aren't affected. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ica8cf9484a6e6fe4362eabb8a9a59fcaf97c1bd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64524 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-20soc/intel/apollolake: Hook up C1e to enhanced_cstatesSean Rhodes
Hook up C1e FSP S UPD which enables enhanced C-states, to enhanced_cstates. This allows it to be enabled in the devicetree with a value of "1" as the default is disabled. C1e exists on both APL and GLK, and has been there since their initial releases. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie803a75ac9fb64a6c21b31baeea7b736e4fbf5fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/64708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20soc/intel/apollolake: Hook up UfsEnabled to devicetreeSean Rhodes
Hook up FSP S UfsEnabled UPD (1d.0) to devicetree. UFS only exist on GLK, and has been there since its initial releases. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I1976bfd340c728c64aaf36d296ac41dcd47bfc61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20soc/intel/apollolake: Allow configuring the LPC IO registersSean Rhodes
Allow configuring the LPC IO registers in the devicetree with: * gen1_dec * gen2_dec * gen3_dec * gen4_dec Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I2a7ab3faf927cda76640227feff4e19017442897 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-10soc/intel/apollolake: Let coreboot set the VendorID and Subsystem IDSean Rhodes
Set all FSP S UPDs that set IDs to 0, which allows them to be set by coreboot. Tested on StarLite Mk IV and LPC now has the correct device ID of 0x31e8, where previously it had 0x7270. The UPDs differ APL and GLK, but the ones configured in this patch have been there since their initial releases. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I034c9dc9d81c4d775dfff0994c9a6be823689b1c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-06-09soc/intel/apollolake: Correct the maximum number of Heci devicesSean Rhodes
Both APL and GLK have 3 Heci devices. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I7dc7afb4d2906838a478083b466b36aa78ec49a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-06-03intel/common/block: move RAPL disabling to common codeUwe Poeche
This patch brings the feature of disabling RAPL to common code. It replaces the current solution for APL and EHL. For special case if RAPL disabling is only working via changes in MCHBAR a new config switch was introduced. Test: Boot mc_apl4/5 with this patch and ensure that the relevant bits in MSR 0x610 are the same as before the patch. Change-Id: I2098ddcd2f19e3ebd87ef00c544e1427674f5e84 Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-06-02soc/intel/common/cpu: Use SoC overrides to set CPU privilege levelSubrata Banik
This patch implements a SoC overrides to set CPU privilege level as the MSR is not consistent across platforms. For example: On APL/GLK/DNV, it's MSR 0x120 and CNL onwards it's MSR 0x151. BUG=b:233199592 TEST=Build and boot google/taeko to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4584516102560e6bb2a4ae8c0d036be40ed96990 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-05-24soc/intel/apollolake: Compare patched FIT pointer with the pre-definedWerner Zeh
Since the FIT pointer is patched at runtime there is no guarantee that the pre-defined one will match the patched one. Add a check and print a warning at runtime if both addresses (pre-defined and patched) do not match as in this case an offline computed hash for the bootblock will differ from the runtime one. Change-Id: Ib1b02ec43af183caa9f5b08b3c485879b423c40f Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-05-24soc/intel/apollolake: Provide FIT pointer in bootblock at build timeWerner Zeh
Before TXE releases the CPU out of reset a pointer to the constructed FIT in SRAM is patched into the loaded bootblock at offset 4G - 64B. Since this patched bootblock gets measured during runtime it will not match the one that is potentially measured from the coreboot image. This patch adds a dedicated fit.c file for Apollo Lake where the FIT pointer is already set to the address TXE will be using at runtime. Test=Compare sha256 sum from coreboot runtime and coreboot.rom of the bootblock and make sure they match. Change-Id: Ia0fd2a19517c70f50ef37e6a2dc2408bae28df10 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-05-24soc/intel/apollolake: Measure bootblock from IFWIWerner Zeh
On Apollo Lake the bootblock is stitched into the IBBL IFWI region at build time. At execution time TXE loads this IBBL into a shared SRAM (which is read-only in this phase) and maps it at 4 GiB - 32 KiB. Then the CPU starts to operate from this shared SRAM as it were flash space. In order to provide a reliable CRTM init, the real executed bootblock code needs to be measured into TPM if VBOOT is selected. This patch adds the needed code to do this. Change-Id: Ifb3f798de638a85029ebfe0d1b65770029297db3 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-05-24security/tpm/crtm: Add a function to measure the bootblock on SoC levelWerner Zeh
On platforms where the bootblock is not included in CBFS anymore (because it is part of another firmware section (IFWI or a different CBFS), the CRTM measurement fails. This patch adds a new function to provide a way at SoC level to measure the bootblock. Following patches will add functionality to retrieve the bootblock from the SoC related location and measure it from there. In this way the really executed code will be measured. Change-Id: I6d0da1e95a9588eb5228f63151bb04bfccfcf04b Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-05-23soc/intel/apollolake: Enable SSDT for fast SPI controllerWerner Zeh
Since the fast SPI controller is hidden on Apollo Lake the OS cannot probe it and is therefore unaware of the reserved resources assigned in coreboot. Select 'FAST_SPI_GENERATE_SSDT' to enable SSDT creation to report the reserved resources to the OS. Change-Id: I23e77a0a01141dc4f299988d19509e6df555a654 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-05-21soc/intel/apollolake: Hook up Sata Hot Plug to device treeSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I37d31598e87e5b625ded3186980e3aba7dcf6440 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-05-21soc/intel/apollolake: Hook up Legacy 8254 TimerSean Rhodes
Hook Timer8254ClkSetting to `legacy_8254_timer` cmos option. If that isn't set, fallback to the `USE_LEGACY_8254_TIMER` Kconfig option. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4f91cc2c8f48e9da47399059386092314b631b08 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-05-18intel/common/block: Provide RAPL and min clock ratio switches in commonUwe Poeche
There are two APL specific config switches for RAPL and min. cpu clock (APL_SKIP_SET_POWER_LIMITS, APL_SET_MIN_CLOCK_RATIO). These switches could be used in future in other CPU platforms. Move them to common code instead of having them just for one SOC. Test: Make sure that the clock ratio (MSR 0x198) and the RAPL settings (MSR0x610) do not change with this patch applied on mc_apl{1,4,5} mainboard. Change-Id: I3d63d1b9b6c96586a3c20bf8c1d8001b1d7c4bed Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-16soc/intel/*: Use SSDT to pass A4GB and A4GSArthur Heymans
GNVS is more fragile as you need to keep struct elements in sync with ASL code. Change-Id: I2cd5e6b56e4a0dbbb11f4a0ac97e8f84d53b90ec Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-05-16soc/intel/apollolake/romstage.c: Remove unused <cpu/x86/pae.h>Elyes Haouas
Found using: diff <(git grep -l '#include <cpu/x86/pae.h>' -- src/) <(git grep -l 'memset_pae\|MEMSET_PAE_\|MAPPING_ERROR\|map_2M_page\|paging_identity_map_addr\|paging_enable_for_car\|paging_set_default_pat\|paging_set_pat\|PAT_ENCODE\|PAT_UC_MINUS\|PAT_WB\|PAT_WP\|PAT_WT\|PAT_WC\|PAT_UC\|paging_set_nxe\|paging_disable_pae\|paging_enable_pae\|paging_enable_pae_cr3' -- src/) Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: If0f69fa8fe4a336b4e4d2a148d1e7a911af3c2c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-15soc/intel/apl: Drop cbfs bootblockArthur Heymans
The bootblock is loaded from IFWI so there is no need to have it in cbfs. Also remove the FIT handling as that is also handled by the IFWI. TESTED: up/squared still boots Change-Id: I8e70e080765dd7306074a8cf71c8795b8fbbb8a2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63225 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-12soc/intel/apl: Write to cbfs regions using intermediate targetsArthur Heymans
This also adds messages when adding the files. Change-Id: Ie812084cc243a18cbc2913804ef2190dd9d6ed9b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-29soc/intel: Decouple HECI disabling interface from HECI disable KconfigSubrata Banik
This patch decouples HECI disabling interface a.k.a SMM or PCR or PMC IPC etc. from DISABLE_HECI1_AT_PRE_BOOT kconfig as Intel ME BWG recommends to disable the CSE PCI device while CSE is in software temporary disable state. BUG=b:228789015 TEST=Able to build google/redrix. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I66abc04d5e195515165a77b0166d004f17d029e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-04-22soc/intel: Remove unused <cbmem.h>Elyes HAOUAS
Change-Id: I529c822c9e952dae6613d3de64f6709e0fd9b385 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-21tpm: Refactor TPM Kconfig dimensionsJes B. Klinke
Break TPM related Kconfig into the following dimensions: TPM transport support: config CRB_TPM config I2C_TPM config SPI_TPM config MEMORY_MAPPED_TPM (new) TPM brand, not defining any of these is valid, and result in "generic" support: config TPM_ATMEL (new) config TPM_GOOGLE (new) config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE) config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE) What protocol the TPM chip supports: config MAINBOARD_HAS_TPM1 config MAINBOARD_HAS_TPM2 What the user chooses to compile (restricted by the above): config NO_TPM config TPM1 config TPM2 The following Kconfigs will be replaced as indicated: config TPM_CR50 -> TPM_GOOGLE config MAINBOARD_HAS_CRB_TPM -> CRB_TPM config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE Signed-off-by: Jes B. Klinke <jbk@chromium.org> Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-08soc/intel/apollolake: Correct enum for PrimaryVideoAdaptor FSP parameterWerner Zeh
Commit 1a4496e79f21 (soc/{apl,glk}: Allow to select the primary graphics device) adds code to set the FSP parameter 'PrimaryVideoAdaptor' based on the enum description of the FspmUpd.h for Apollo Lake. Unfortunately, the comment in the header file does not match the implementation in the FSP and hence setting PrimaryVideoAdaptor to 'GPU_PRIMARY_IGD' will be treated as if the selection was 'GPU_PRIMARY_PCI'. This in turn leads to Linux gfx driver issues for earlier driver implementations. This commit corrects the enum values for the FSP parameter to match the implementation. TEST=Boot into Linux on mc_apl1 and verify that graphics works. Change-Id: Iedbc144fa809f6d4587f5223b235ee95579c48f7 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-03-31Kconfig: Select UDK2017Patrick Rudolph
On platforms using UDK2015 select UDK2017 instead. This allows to drop UDK2015 headers. Tested using timeless builds: The produced binaries are identical. Change-Id: Ia6032c6520ec889cd63655db982d9bfa476dc24d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-03-29soc/intel: Move `pmc_clear_pmcon_sts()` into IA common codeSubrata Banik
This patch moves `pmc_clear_pmcon_sts` function into common code and remove SoC specific instances. Accessing PMC GEN_PMCON_A register differs between different Intel chipsets. Typically, there are two possible ways to perform GEN_PMCON_A register programming (like `pmc_clear_pmcon_sts()`) as: 1. Using PCI configuration space when GEN_PMCON_A is a PCI configuration register. 2. Using MMIO access when GEN_PMCON_A is a memory mapped register. SoC users to select `SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION` Kconfig to perform GEN_PMCON_A register programming using PMC MMIO. BUG=b:211954778 TEST=Able to build brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8d15f421c128630f928a1b6a7e2840056d68d7b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeff Daly <jeffd@silicom-usa.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-03-14soc/intel/common: Implement error codes for for heci_send_receive()Sridhar Siricilla
The patch implements below changes: 1. Implements different error codes and use them in appropriate failure scenarios of below functions: a. heci_send() b. recv_one_message() c. heci_receive() 2. As heci_send_receive() is updated to return appropriate error codes in different error scenarios of sending and receiving the HECI commands. As the function is updated to return 0 when success, and non-zero values in the failure scenarios, so all caller function have been updated. BUG=b:220652101 TEST=Verified CSE RX and TX APIs return error codes appropriately in the simulated error scenarios. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ibedee748ed6d81436c6b125f2eb2722be3f5f8f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62299 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-10soc/apollolake: Hook up VTD to CMOSSean Rhodes
Hook up vtd_enable to CMOS value of "vtd". Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I16b43f0489f652d650e820c36b2b9bea61cf3c8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-10soc/apollolake: Correct SMBus interruptSean Rhodes
This solved the error: i801_smbus 0000:00:1f.1: can't derive routing for PCI INT A i801_smbus 0000:00:1f.1: PCI INT A: not connected i801_smbus 0000:00:1f.1: SPD Write Disable is set i801_smbus 0000:00:1f.1: SMBus using polling Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Idebd581b7ed6d193d83340b7dc94248df43525c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-09soc/apollolake: Hook up CnviMode to devicetreeSean Rhodes
Hook PCH_DEVFN_CNVI (0c.0) to CnviMode. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I8b51e98952a39bd432e9bc63eea57a40dd6cf106 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andy Pont <andy.pont@sdcsystems.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-07src: Make PCI ID define names shorterFelix Singer
Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with PCI_{DID,VID}_ using the commands below, which also take care of some spacing issues. An additional clean up of pci_ids.h is done in CB:61531. Used commands: * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g' * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g' Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-02-25arch/x86: factor out and commonize HPET_BASE_ADDRESS definitionFelix Held
All x86 chipsets and SoCs have the HPET MMIO base address at 0xfed00000, so define this once in arch/x86 and include this wherever needed. The old AMD AGESA code in vendorcode that has its own definition is left unchanged, but sb/amd/cimx/sb800/cfg.c is changed to use the new common definition. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifc624051cc6c0f125fa154e826cfbeaf41b4de83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-02-24soc/apollolake: Allow configuring individual USB ports on GLKSean Rhodes
Allow configuring the limited fields that FSP-S provides. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I56c37338eaa978fdb2c63807331493e8aecbdf60 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-18soc/intel/apollolake: Create alias for GEN_PMCON1 as GEN_PMCON_ASubrata Banik
This patch creates alias for GEN_PMCON_A to maintain parity with other IA SoC PMC register definitions. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Id9a23c58a325cb544c50cbda432fe3117eea22fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/61984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-18drivers/fsp/fsp2_0: Rework FSP Notify Phase API configsSubrata Banik
This patch renames all FSP Notify Phase API configs to primarily remove "SKIP_" prefix. 1. SKIP_FSP_NOTIFY_PHASE_AFTER_PCI_ENUM -> USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM 2. SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT -> USE_FSP_NOTIFY_PHASE_READY_TO_BOOT 3. SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE -> USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE The idea here is to let SoC selects all required FSP configs to execute FSP Notify Phase APIs unless SoC deselects those configs to run native coreboot implementation as part of the `.final` ops. For now all SoC that uses FSP APIs have selected all required configs to let FSP to execute Notify Phase APIs. Note: coreboot native implementation to skip FSP notify phase API (post pci enumeration) is still WIP. Additionally, fixed SoC configs inclusion order alphabetically.  BUG=b:211954778 TEST=Able to build and boot brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib95368872acfa3c49dad4eb7d0d73fca04b4a1fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/61792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-15soc/intel/apollolake: Fix overlapping ACPI resource rangesMatt DeVillier
The address space allotted to MCRS in the northbridge needs to be exclusive of the address space allotted to the GPIO controllers in the southbridge, otherwise Windows complains of overlapping resource ranges and disables the GPIO controllers. To prevent overlap, use CONFIG_PCR_BASE_ADDRESS to set the upper bound of MCRS rather than MMCONF. Test: boot Windows 10/11 on google/{reef,ampton} and verify that GPIO controllers are indicated as without fault in Device Manager. Change-Id: I2117054edb448e717b7cbe80958c9c4e6c996e2b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: CoolStar Organization <coolstarorganization@gmail.com>
2022-02-15soc/intel/apollolake: Add function to clear PMCON status bitsSubrata Banik
This patch adds an SoC function to clear GEN_PMCON_A status bits to align with other IA coreboot implementations. BUG=b:211954778 TEST=None. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I982f669b13f25d1d0e6dfaec2fbf50d3200f74fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/61651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-02-15soc/apollolake: Make IO decode / enable register configurableSean Rhodes
This allows the one 32bit register to be configured in the devicetree in the same way that Skylake can be. i.e. register "lpc_ioe". Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I598baca0f31b5350a4e6fdb7b7356fa6fb2d71ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/61195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-12soc/intel/apl: Use Kconfig to enable CseRbpSean Rhodes
This patch makes SKIP_CSE_RBP=y default for Apollo Lake if Boot Device is memory mapped and ensures SkipCseRbp UPD is guarded against this config. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ifd01a25443e2582a90529e55be8d34a88342a103 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-07soc/intel/apollolake: Convert to ASL 2.0Elyes HAOUAS
Change-Id: Ieb362b5be05421b6ad2b2a3126c2943b7d55d135 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-05cpu/x86/lapic: Move LAPIC configuration to MP initKyösti Mälkki
Implementation for setup_lapic() did two things -- call enable_lapic() and virtual_wire_mode_init(). In PARALLEL_MP case enable_lapic() was redundant as it was already executed prior to initialize_cpu() call. For the !PARALLEL_MP case enable_lapic() is added to AP CPUs. Change-Id: I5caf94315776a499e9cf8f007251b61f51292dc5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-04soc/intel/{adl, common}: Add routines into CSE IA-common codeSubrata Banik
This patch adds routines to keep CSE and other HECI devices into the lower power device state (AKA D0I3). - cse_set_to_d0i3 => Set CSE device state to D0I3 - heci_set_to_d0i3 => Function sets D0I3 for all HECI devices Additionally, creates a config `MAX_HECI_DEVICES` to pass the HECI device count info from SoC layer to common CSE block. As per PCH EDS, the HECI device count for various SoCs are: ADL/CNL/EHL/ICL/JSL/TGL => 6 (CSE, IDE-R, KT, CSE2, CSE3 and CSE4) APL => 1 (CSE) SKL/Xeon_SP => 5 (CSE, IDE-R, KT, CSE2 and CSE3) BUG=b:211954778 TEST=Able to build and boot Brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie32887196628fe6386896604e50338f4bc0bedfe Reviewed-on: https://review.coreboot.org/c/coreboot/+/61518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-03soc/intel/apollolake: Rename PWRMBASE macro and functionSubrata Banik
This patch ensures PWRMBASE macro name and function to get PWRMBASE address on APL SoC is aligned with other IA SoC. PMC_BAR0 -> PCH_PWRM_BASE_ADDRESS read_pmc_mmio_bar() -> pmc_mmio_regs() Additionally, make `pmc_mmio_regs` a public function for other IA common code may need to get access to this function. BUG=None TEST=None Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3a61117f34b60ed6eeb9bda3ad853f0ffe6390f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-02soc/intel/apollolake: Use PCR write to disable HECI1Subrata Banik
Set the SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR config for Apollo Lake to disable HECI1 device using PCR writes. BUG=none TEST=None Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8df9544296f0bea095c5415805a596cb5b36885e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-02-02soc/intel/common/cse: Rework heci_disable functionSubrata Banik
This patch provides the possible options for SoC users to choose the applicable interface to make HECI1 function disable at pre-boot. `SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_SBI` config is used for disabling heci1 using non-posted sideband write (inside SMM) after FSP-S sets the postboot_sai attribute. Applicable from CNL PCH onwards. `SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PMC_IPC` config is used for disabling heci1 using PMC IPC command `0xA9`. Applicable from TGL PCH onwards. `SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PCR` config is used for disabling heci1 using private configuration register (PCR) write. Applicable for SoC platform prior to CNL PCH. Additionally, add PID_CSME0 macro for SKL, Xeon_SP and APL to fix the compilation failure. Finally, rename heci_disable() function to heci1_disable() to make it more meaningful. BUG=none TEST=Able to build and boot brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7e0bab0004013b999ec1e054310763427d7b9348 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-02-01soc/intel/appololake: Allow to configure SATA ALPM via devicetreeMario Scheithauer
Add a devicetree option to disable SATA Aggressive Link Power Management. ALPM is a method of saving power. The corresponding FSP-S UPD parameter is enabled by default. It may be that this feature is unwanted, for example for a real-time system. Therefore, allow to disable ALPM using the devicetree. Change-Id: Ica8920a87ebebe83f5d8cb4d6c8c0a6105e183e4 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-01-19soc/intel/common/cpu: Use SoC overrides to get CPU privilege levelSubrata Banik
This patch implements a SoC overrides to check CPU privilege level as the MSR is not consistent across platforms. For example: On APL/GLK/DNV, it's MSR 0x120 and CNL onwards it's MSR 0x151. BUG=b:211573253, b:211950520 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I515f0a3548bc5d6250e30f963d46f28f3c1b90b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-11soc/intel/apl: Use Kconfig to disable HECI1Subrata Banik
This patch makes DISABLE_HECI1_AT_PRE_BOOT=y default for Apollo Lake and ensures disable_heci1() is guarded against this config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7ac0cad97fcd42b2c6386693319d863352356864 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-01-11soc/intel/apl: Rework on CPU privilege level implementationSubrata Banik
This patch migrates common code API into SoC specific implementation to drop CPU privilege level as the MSR is not consistent across platforms. For example: On APL/GLK, it's MSR 0x120 and CNL onwards it's MSR 0x151. Also, include `soc/msr.h` in cpu.h to fix the compilation issue. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0b6f39509cc5457089cc15f28956833c36b567ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/60898 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-25 19:13:11 +0000