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authorSean Rhodes <sean@starlabs.systems>2022-07-28 20:55:40 +0100
committerSean Rhodes <sean@starlabs.systems>2022-12-22 21:17:04 +0000
commit759aa17e79c4096e8fe3cee9fc04e899059e9f76 (patch)
treeba12e6ddee78280e2d8c342203a2e1a205c63e8c /src/soc/intel/apollolake
parenta49cd32da028d60e52d9e8078514c9a09a005710 (diff)
soc/intel/apollolake/acpi: Remove TOUUD as it is not used
Remove Top of Upper Usable DRAM Low from MCHC as it isn't needed. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ifdd8c9ba61c5b1c6b154369413470e431ce8f5b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66231 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/apollolake')
-rw-r--r--src/soc/intel/apollolake/acpi/northbridge.asl2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl
index b1ed3e56b4..0bea341845 100644
--- a/src/soc/intel/apollolake/acpi/northbridge.asl
+++ b/src/soc/intel/apollolake/acpi/northbridge.asl
@@ -17,8 +17,6 @@ Device (MCHC)
, 25,
PXBR, 11, /* PCI Express Base Address */
- Offset (0xA8),
- TUUD, 64, /* Top of Upper Used Memory */
Offset(0xB4),
BGSM, 32, /* Base of Graphics Stolen Memory */
Offset(0xBC),