drivers/fsp/fsp2_0: Rework FSP Notify Phase API configs

This patch renames all FSP Notify Phase API configs to primarily remove
"SKIP_"  prefix.

1. SKIP_FSP_NOTIFY_PHASE_AFTER_PCI_ENUM ->
          USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
2. SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT ->
          USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
3. SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE ->
          USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE

The idea here is to let SoC selects all required FSP configs to execute
FSP Notify Phase APIs unless SoC deselects those configs to run native
coreboot implementation as part of the `.final` ops.

For now all SoC that uses FSP APIs have selected all required configs
to let FSP to execute Notify Phase APIs.

Note: coreboot native implementation to skip FSP notify phase API (post
pci enumeration) is still WIP.

Additionally, fixed SoC configs inclusion order alphabetically. 

BUG=b:211954778
TEST=Able to build and boot brya.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib95368872acfa3c49dad4eb7d0d73fca04b4a1fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

1 files changed, 17 insertions, 14 deletions

diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index f9ad4d63f0..91d203eb2c 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -41,18 +41,27 @@ config CPU_SPECIFIC_OPTIONS
 	select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS
 	select FSP_STATUS_GLOBAL_RESET_REQUIRED_5
 	select GENERIC_GPIO_LIB
-	select INTEL_DESCRIPTOR_MODE_CAPABLE
-	select HAVE_SMI_HANDLER
+	select HAVE_ASAN_IN_ROMSTAGE
+	select HAVE_CF9_RESET_PREPARE
+	select HAVE_FSP_GOP
+	select HAVE_FSP_LOGO_SUPPORT
 	select HAVE_INTEL_FSP_REPO if !SOC_INTEL_GEMINILAKE
+	select HAVE_SMI_HANDLER
+	select INTEL_DESCRIPTOR_MODE_CAPABLE
+	select INTEL_GMA_ACPI
+	select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
+	select INTEL_GMA_SWSMISCI
 	select MRC_SETTINGS_PROTECT
 	select MRC_SETTINGS_VARIABLE_DATA
-	select NO_XIP_EARLY_STAGES
 	select NO_PM_ACPI_TIMER
+	select NO_UART_ON_SUPERIO
+	select NO_XIP_EARLY_STAGES
 	select PARALLEL_MP_AP_WORK
 	select PCIEXP_ASPM
 	select PCIEXP_COMMON_CLOCK
 	select PCIEXP_CLK_PM
 	select PCIEXP_L1_SUB_STATE
+	select PLATFORM_USES_FSP2_0
 	select PMC_INVALID_READ_AFTER_WRITE
 	select PMC_GLOBAL_RESET_ENABLE_LOCK
 	select REG_SCRIPT
@@ -97,22 +106,16 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK_CSE
 	select SOC_INTEL_COMMON_BLOCK_SMBUS
 	select SOC_INTEL_COMMON_FSP_RESET
+	select SOC_INTEL_COMMON_RESET
 	select SOC_INTEL_NO_BOOTGUARD_MSR
 	select SOUTHBRIDGE_INTEL_COMMON_SMBUS
-	select UDELAY_TSC
 	select TSC_MONOTONIC_TIMER
-	select PLATFORM_USES_FSP2_0
+	select UDELAY_TSC
 	select UDK_2015_BINDING if !SOC_INTEL_GEMINILAKE
 	select UDK_2017_BINDING if SOC_INTEL_GEMINILAKE
-	select SOC_INTEL_COMMON_RESET
-	select HAVE_CF9_RESET_PREPARE
-	select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
-	select HAVE_FSP_GOP
-	select HAVE_FSP_LOGO_SUPPORT
-	select NO_UART_ON_SUPERIO
-	select INTEL_GMA_ACPI
-	select INTEL_GMA_SWSMISCI
-	select HAVE_ASAN_IN_ROMSTAGE
+	select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
+	select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
+	select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
 	# This SoC does not map SPI flash like many previous SoC. Therefore we
 	# provide a custom media driver that facilitates mapping
 	select X86_CUSTOM_BOOTMEDIA