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2024-07-22soc/intel/alderlake/tcss: Add definition of IOM_READY bitMichał Żygowski
Add definition of the IOM_READY bit in the IOM_TYPEC_STATUS_1 register. Needed by Protectli VP66XX boards to poll for this bit for about 2 seconds before FSP Silicon Init to have USB functionality. ME is supposed to start fetching and executing the TCSS IPs FW right after DRAM Init Done message, which happens after MRC. For most platforms the time interval between the end of MemoryInit and start of SiliconInit is enough for IOM_READY to get set. TEST=Poll the IOM_READY bit on VP66XX platform and observe the TCSS XHCI is up in lspci. Change-Id: If868a77852468ebb73526b1571191cbdeb1804b9 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83356 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-18soc/intel/alderlake: Switch to common eSPI headerSubrata Banik
This patch updates Alder Lake code to use the common eSPI header file (`intelpch/espi.h`) instead of the SoC-specific one. BUG=none TEST=Builds successfully for google/redrix. Change-Id: Ib4452547325042de48ee4fca3d3910a031b56b64 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83484 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-18soc/intel/alderlake: Use common CAR API for cache reportingSubrata Banik
Replace the SoC-specific `report_cache_info()` function with the common `car_report_cache_info()` API from `car_lib`. This promotes code reuse and reduces SoC-specific implementation for cache reporting. BUG=none TEST=Builds and boots successfully on google/marasov platform. Change-Id: I18be2c33dbe5186643af52823eb2fb185a296909 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83481 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-13soc/intel/alderlake: Fix system hang by enabling SMI handlingJamie Chen
Issue: System hang occurred due to unhandled SPI synchronous SMI, triggered by LOCK_ENABLE bit and WPD assertion. Solution: Enabled SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE configuration to allow the system to handle and clear SPI synchronous SMI. BUG=b:350623902 TEST=reboot test on 40 google/xol by ODM, all passed w/o hang. Change-Id: I4c14b1e3d537e46e671e950c91c9d0042fe26836 Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83432 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: SH Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-by: Edward Doan <edoan@chromium.org>
2024-07-12soc/intel: Adapt crashlog IP to also support 64-bitSowmya Aralguppe
This patch extends the crashlog IP support beyond 32-bit mode to support Intel future generation SoCs, which may require crashlog support for 64-bit architectures. uintptr_t data type is used for Address pointers and void* for dereferencing BUG=b:346676856 TEST=Successfully built Meteor Lake (rex) and tested for google/rex0 and google/rex64 images. Change-Id: I552257d3770abb409e2dcd8a13392506b5e7feb7 Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83106 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-26acpi: Rename acpi_create_dmar_drhdShuo Liu
For most of SoCs, DRHD is by default with the size of 4KB. However, larger sizes are allowed as well. Rename acpi_create_dmar_drhd to acpi_create_dmar_drhd_4k to support the default case while a later patch will re-add acpi_create_dmar_drhd with a size parameter. TEST=intel/archercity CRB Change-Id: Ic0a0618aa8e46d3fec2ceac7a91742122993df91 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-06-16soc/intel/alderlake: Use the RPL-P IoT FSP if desiredBenjamin Doron
This change also drops a duplicated config default line, which might be why this was omitted. Change-Id: I2b4c8b316adaadec3e49d5162b37b37629331b06 Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83086 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-13soc/intel/adl: Skip RW CBFS ucode update if RO is lockedSubrata Banik
This patch eliminates coreboot from loading microcode from RW CBFS (when the RO descriptor is locked, which indicates a fixed RO image) because the kernel can already patch the microcode on BSPs and APs while booting to OS. This may be a chance to lower the burden on the AP FW side because patching microcode on in-field devices is subject to firmware updates, which are rarely published and, if required, must go through the firmware qualification testing procedure (which is costly, unlike kernel updates for ucode updates). 1. The FIT loads the necessary microcode from the RO during reset. 2. Reloading microcode from RW CBFS impacts boot time (~60ms, core-dependent). 3. The kernel can still load microcode updates. ChromeOS devices leverage RO+RW-A/RW-B booting. The RO's microcode is sufficient for initial boot, and the kernel can apply updates later. BUG=none TEST=Verified boot optimization; in-field devices skip RW-CBFS microcode loading when RO is locked. Change-Id: I68953d45d3624aba0a3be28bc7b266b7621ddcc4 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82999 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-08soc/alderlake/romstage: Set UsbTcPortEnPreMem UPD based on devicetreeMichał Żygowski
The UsbTcPortEn UPD for FSP-S is being set in ramstage, however the equivalent FSP-M UPD, the UsbTcPortEnPreMem, was not being set. Following the Meteor Lake example, set the UsbTcPortEnPreMem UPD as well for Alder Lake. Setting this FSP-M UPD will cause FSP to properly program sideband use BSSB_LSx pins for the enabled Type-C ports. Required for proper DCI debug and TCSS initialization flow. Change-Id: If3b79167ec1769ddfb7d28a6c78a3e80bd10afe7 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80500 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-06-07soc/intel/alderlake: select Kconfig MRC_CACHE_USING_MRC_VERSIONRonak Kanabar
This patch introduces support for storing the MRC cache based on the MRC version for both ADL-N and TWL platforms. It select the MRC_CACHE_USING_MRC_VERSION option when client SOC_INTEL_ALDERLAKE_PCH_N is chosen. BUG=b:296433836 Change-Id: Icc7e4ecd84a7d2818d54acc6ac5d0592544bb9ce Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81038 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Brandon Weeks <bweeks@google.com>
2024-06-07intel/alderlake/Kconfig: Use vendorcode headers for Client ADL-N FSPRonak Kanabar
This patch is to switch Client ADL-N FSP headers to vendorcode from IOT headers. Also guard IOT headers & bin path with FSP_TYPE_IOT Kconfig. BUG=b:296433836 TEST=Able to build and boot google/nivviks Change-Id: I1ffcc3f284c213ff0533de3a0e228aacf523b380 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-06-07soc/intel/alderlake: Guard PchPcieClockGating & PchPciePowerGating UPDsRonak Kanabar
PchPcieClockGating & PchPciePowerGating UPDs are not available for ADL_N FSP headers. Add guard to Avoid PchPcieClockGating & PchPciePowerGating programming for ADL_N FSP. Change-Id: I2f1625038896b07c354498fe431cad97fb9b5bdb Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82917 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-05-09mb/google/brox: Sending End of Post (EOP) asynchronouslyKarthikeyan Ramasubramanian
Currently EOP message is sent to CSE late in the boot flow. Instead send it asynchronously to save ~10 ms in boot time. BUG=b:337330958 TEST=Build Brox BIOS Image and boot to OS. Change-Id: I229d16a5dcd072958db3f59a9c364bf7508b3047 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-30soc/intel/alderlake: Default to 512 for DIMM_SPD_SIZEFelix Singer
Alderlake and Raptorlake SoCs support DDR4 and DDR5, which have a total SPD size of 512 bytes. Set this as the default and remove the setting from mainboard Kconfigs. Change-Id: I8703ec25454a0cd55a3de70f73d2117285a833ae Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82115 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-23soc/intel/alderlake: Add Twinlake graphics device IDsSowmya V
Add the graphics device IDs for Twinlake platform based on Platform External Design Specification. Document ID: 645548 BUG=b:326901448 TEST=Build tivviks and verify the IGD IDs. Change-Id: Ide008d5c5302bd589784bc917a2610c42a0fdee4 Signed-off-by: Sowmya V <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82038 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-04-11tree: Drop unused <timestamp.h>Elyes Haouas
Change-Id: Ic690a7543f8a1e072650917d7a1e9e3b9dc371a3 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-04-11soc/intel/alderlake: Support missing CLKREQ workaround on RaptorLake FSPBenjamin Doron
IoT variants of the RaptorLake FSP support the `PchPciePowerGating` and `PchPcieClockGating` UPDs, so, remove the preprocessor check that only enabled it for AlderLake FSPs. Change-Id: I583a4b257b72f992fdb6390d00e187d04a749177 Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81803 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-09soc/intel/alderlake: Fix non-local header treated as localElyes Haouas
Change-Id: I93e6989633b9ac1b2738b812e3f8b442ecfdcbf0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81813 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-09tree: Drop unused <delay.h>Elyes Haouas
Change-Id: I265e427254ce9f735e65b0631c43f98bc778a34f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81812 Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-04-01soc/intel/alderlake: Remove FSP_PUBLISH_MBP_HOB config for RPLKilari Raasi
The RPL FSP currently uses HECI commands to retrieve the chipset initialization version because the MBP HOB creation is disabled (SkipMbpHob=1). This has resulted in an approximate 150ms increase in boot time. Investigations are ongoing to determine the cause of the delay when using HECI commands. As an interim solution, this patch sets SkipMbpHob=0, enabling the use of MBP HOB or acquiring the chipset initialization version, which is expected to reduce the boot time. BUG=b:328430167 TEST= Able to build,boot and collect boot time data of brya. With this patch: 963:returning from FspMultiPhaseSiInit 1,337,481 (249,046) Without this patch: 963:returning from FspMultiPhaseSiInit 1,496,268 (408,194) Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Change-Id: I8a99a57b644732074e41051d99e63576f1edd229 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2024-03-30soc/intel: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: I79b93b0ca446411e2a1feb65d00045e3be85ee8a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-03-24soc/intel/alderlake: Attach timestamp around eSOL callSubrata Banik
This patch adds timestamp start/end entries around the eSOL implementation to track the panel initialization time while rendering the eSOL screen. TEST=Able to build and boot google/omnigul. 555: started early sign-off life (eSOL) notification 643,694 (40) 556: finished early sign-off life (eSOL) notification 1,072,143 (428,449) Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I51c04fc4bd2540b3f42e2f896178521d297ef246 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-22soc/intel/alderlake: select UDK_202111_BINDING for ADL-NRonak Kanabar
ADL-N FSP uses 202111 Edk2. select UDK_202111_BINDING Kconfig for ADL-N SoC. BUG=b:296433836 TEST=Able to build and boot google/crassk. Change-Id: If277ede4307515035389cd0e9d34c15cc80f278c Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80274 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-21soc/intel/adl: Guard TWL SoC missing UPDs for build integritySubrata Banik
Adds config-based guards for Usb4CmMode and CnviWifiCore UPDs, specific to Twin Lake SoCs (SOC_INTEL_TWINLAKE). Prevents compilation errors due to missing UPD definitions. BUG=b:330654700 TEST=Able to build google/tivviks. Change-Id: I6e0a9a7536df6295e23bf06003539e56bb98a311 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81376 Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-09soc/intel/alderlake: Add Raptor Lake System Agent Device IDsLean Sheng Tan
Add System Agent IDs for Raptor Lake SKUs based on RPL Datasheet (Doc ID: 743844) & EDS Vol 1 (Doc ID: 640555). Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I805040c65852742f1bbc43b443e115bcb0a930aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/81115 Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-09soc/intel/alderlake: Remove the guard for CnviWifiCoreSean Rhodes
The CnviWifiCore UPD exists for ADL (version 4263) and RPL (version 4415). Remove the guard so it is set correctly. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9943ee43a442a43d75e78d1551e46dcea39db357 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81079 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-08drivers/intel/fsp2_0: Add "silicon" to the multiphase callback nameJeremy Compostella
The `platform_fsp_multi_phase_init_cb' callback is specific to FSP-S, let's rename it 'platform_fsp_silicon_multi_phase_init_cb' to avoid any confusion. Change-Id: I86b69e2069f08023e6f48464f6df4593710aa9ee Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-02-26soc/intel/alderlake: Add kconfig for Twin LakeKapil Porwal
Mainboards using Intel Twin Lake (TWL) SoC shall select SOC_INTEL_TWINLAKE. BUG=none BRANCH=firmware-nissa-15217.B TEST=Build and boot Google/Yaviks with Twin Lake kconfig enabled Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ie4c5d137ee54512313344f853e7ca66d1fd25003 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80688 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-23soc/intel/adl: Set slp-s0 counter frequencyMarx Wang
System sleep time (SLP_S0 signal asserted) is measured in ticks, for Alder Lake soc in 122us (i.e. ~8197Hz) granularity/ticks. BUG=b:301854636 TEST=/sys/devices/system/cpu/cpuidle/ low_power_idle_system_residency_us" will show system idle residency time Change-Id: I449f7ed0d9ef891ae5266e8fd784a063a75e38eb Signed-off-by: Marx Wang <marx.wang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-02-22soc/intel/alderlake: Remove Alder Lake M SKUSean Rhodes
ADL-M is not commercially available, so it can be removed. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If769989f7a0434e32ebbcc8eac9b965b70ca71ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/80614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-02-22soc/intel/alderlake: Sync UPD Usb4CmMode with KconfigSean Rhodes
The ACPI is adjusted based on SOFTWARE_CONNECTION_MANAGER, so set the UPD to match this to avoid the connection type being mismatched. If it's mismatched, the TBT port will time out. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I8a99db165301ce08caf55aac0e33ca1994559d62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80486 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-02-21soc/intel/alderlake: Include ADL-N ID 5Sean Rhodes
This patch adds support for using ADL N 4-core MCH ID 0x4618. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I7b9fc64ccf8e2401dcd55607e8f09b348efb3182 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80166 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-19soc/intel/alderlake: Include ADL-N ID 5 0x4618Sean Rhodes
This patch adds support for using ADL N 4-core MCH ID 0x4618. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3e4855ce93666c54ab35def9b58e4b13bc9a8672 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-18soc/intel/alderlake/acpi: Drop ACPI stub for SATA deviceMatt DeVillier
This is now generated by acpigen in the common/block/sata module. Change-Id: Ic45a059f47a090aa1993e83884408a82826b30cf Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-02-18soc: Add SPDX license headers to Kconfig filesMartin Roth
Change-Id: Ie7bc4f3ae00bb9601001dbb71e7c3c84fd4f759a Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80596 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-13soc/intel/alderlake: Leverage IA common code for range calculationsSubrata Banik
Improves code maintainability and potentially reduces redundancy by using the IA common implementation. Additionally, drop the unused macros from SoC local. TEST=Build and boot successful on google/marasov. Change-Id: I290fea99f04cfc9f18e5f1435ed07de42995869f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80403 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-12soc/intel/cmn/sa: Refactor SA common codeSubrata Banik
Leverages common SA header definitions for Host Bridge registers. Renames DSM_BASE_ADDR_REG to BDSM and DPR_REG to DPR for brevity. Additionally, made some minor code alignment corrections while adding newer macros in the header file. TEST= Build and boot successful on google/screebo. Change-Id: I476f213d75a0978336b3749a5ba1499107eb2238 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-01-31include/device/device.h: Remove CHIP_NAME() macroNicholas Sudsgaard
Macros can be confusing on their own; hiding commas make things worse. This can sometimes be downright misleading. A "good" example would be the code in soc/intel/xeon_sp/spr/chip.c: CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev, This appears as CHIP_NAME() being some struct when in fact these are defining 2 separate members of the same struct. It was decided to remove this macro altogether, as it does not do anything special and incurs a maintenance burden. Change-Id: Iaed6dfb144bddcf5c43634b0c955c19afce388f0 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80239 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-24soc/intel: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ib479b93b7d0b2e790d0495b6a6b4b4298a515d9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/80073 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-17Reland "Kconfig: Bring HEAP_SIZE to a common, large value"Patrick Georgi
This reverts commit acbc4912375085a099c2427def464d6e481f2a90. Reason for revert: CB:79525 fixes the issue that led to the revert by not maintaining the heap in the SMM-stored copy of ramstage at all. Change-Id: I3c8ef785486d275c9341859d34fce12253bd2bb9 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80023 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-26soc/intel/alderlake: Make C1e configurableSean Rhodes
Make it possible to enable C1e from the devicetree by adding `c1e_enable`. C1e was disabled by ea2a38be323173075db3b13729a4006ea1fef72d for all RPL SOCs to reduce noise. This will ensure that boards that disabled it based on CPUID are unchanged. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I758621393cb39345c2ba7b19a32872e84e1c5a19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77088 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-14vc/intel/raptorlake: Updating the FSP v4301.01 headers to Standard pathKulkarni, Srinivas
Move the existing FSP 4301.01 headers for Raptor Lake out of subdirectory called 43101.01 to follow standard process. Change-Id: I710f373acd37e9e0f8b50084a1a7e9fbda816e8c Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-12-04soc/intel/alderlake: Update LidStatus UPD dynamicallySubrata Banik
This patch ensures that the LidStatus UPD is passed a dynamic value, rather than always passing 1 (CONFIG_RUN_FSP_GOP enabled) for FSP 2.0 devices. Problem statement: * FSP-S GFX PEIM initializes the on-board display (eDP) even when the LID is physically closed, because LidStatus is always set to 1. * FSP-S skips external display initialization even when the LID is closed. Solution: * FSP-S GFX PEIM module understands the presence of an external display if LidStatus is not set, and tries to probe the other display endpoint. * Statically passing LidStatus as always enabled (aka 1) does not illustrate the exact device scenarios, so this patch updates LidStatus dynamically by reading the EC memory map offset. BUG=b:313886118 TEST=Able to build and boot google/marasov to redirect the display using external HDMI monitor while LID is closed. Change-Id: Idb1d71bd54837630f36d43a45effc53d35f9cb70 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79352 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-10soc/intel/alderlake: Allow using FSP repo for all RPL-S platformsMichał Żygowski
The Client FSP for Raptor Lake-S is present on the Intel FSP repository, so there is no need to restrict Raptor Lake-S FSP binary repository to IoT only. TEST=Build and boot MSI PRO Z790-P Change-Id: I77aecd6e2d753732bf6358afe2c7ea0491348387 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-10soc/alderlake: Fix order of defaults in FSP_HEADER_PATHMichał Żygowski
The combination of SOC_INTEL_RAPTORLAKE_PCH_S and FSP_TYPE_IOT is currently broken. By default, e.g. for MSI PRO Z790-P, the FSP_HEADER_PATH does not match the default FSP_FD_PATH. For headers the client FSP is selected, while for the FD file, IoT FSP binary is chosen. The order of default for both headers and FD file must be the same to match the headers and binaries. TEST=Build default MSI PRO Z790-P config and see that FSP_HEADER_PATH matches FSP_FD_PATH FSP variant-wise. Change-Id: I8db5ea10c2986ff8d3fa7d616b3f1617d05f0260 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78410 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-07Revert "Kconfig: Bring HEAP_SIZE to a common, large value"Patrick Georgi
This reverts commit 44a48ce7a46c36df69f7b2cf3552bf10fa5f61b6. Reason for revert: It breaks wakeup from suspend on a bunch of boards. While this approach of eyeballing "correct" values by chipset _should_ be fixed, it should also be accompanied by compile time verification that the memory map works out. Since nobody seems to care enough, let's just revert this, instead of keeping the tree broken for a bunch of configurations. Change-Id: I3cd73b6ce8b15f06d3480a03ab472dcd444d7ccc Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78850 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-11-04soc/intel/alderlake: Add missing min sleep state for DPTF deviceMatt DeVillier
Add an entry in the min_pci_sleep_states array for SA_DEVFN_DPTF, to correct warning in cbmem log: [WARN] unknown min d_state for PCI device 00:04.0 TEST=build/boot google/brya (banshee), verify warning not present in cbmem log, verify entry for DPTF device in ACPI LPI constraint list. Change-Id: I2a9976b065f08e4acd31c3deca13c5278f031a90 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78877 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-11-02drivers/intel/gma/opregion: Use CBFS cache to load VBTJeremy Compostella
Thanks to x86 CBFS cache support, we can leverage cbfs_map() function to load the VBT binary regardless of if it is compressed or not. Change-Id: I1e37e718a71bd85b0d7dee1efc4c0391798f16f7 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-11-02soc/intel/*: Correct ACPI device name for eMMCMatt DeVillier
The ACPI name of any device needs to match the name used for generating the S0i3 LPI constraint list, which comes from soc_acpi_name() for each SoC. The names used for the eMMC controller do not match, which will lead to broken ACPI tables since the LPI constriant will reference an ACPI device which does not exist. Some OSes tolerate this better than others, but it should still be corrected. TEST=build/boot google/{hatch,volteer, brya}, dump ACPI and verify no invalid device names referenced. Change-Id: Icbc22b6b2a84bbe73f1b09083f27081612db5eba Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78825 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-20device/device.h: Rename pci_domain_scan_busArthur Heymans
On all targets the domain works as a host bridge. Xeon-sp code intends to feature multiple host bridges below a domain, hence rename the function to pci_host_bridge_scan_bus. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I4e65fdbaf0b42c5f4f62297a60d818d299d76f73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78326 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-10-19soc/intel/alderlake: Fix incorrect microcode commentsMichał Żygowski
The microcode for RPL-S C0 and H0 is actually available, however, the name of the file contained a typo: 06-b7-05 vs 06-bf-05. Fix the typos in the comments. Moreover, the ADL-S C0/H0 microcode file 06-97-05 has the same sha256 sum as the equivalent RPL-S C0/H0 microcode file 06-bf-05. The sha256 sum of ADL-S/RPL-S C0/H0 microcode on intel-microcode tag microcode-20230808: 5d8d4a4d5456c43b7cc04937c80aec094ccbf3bd89f34ffa5182913ef944a9f9 Update the comments to correctly indicate supported CPU steppings. Change-Id: I4c848e0dfc40f6c8e26a9b31e7c4cf4c5a09128f Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78413 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-19vc/intel/raptorlake: Use FSP v4301.01 headers for GoogleNick Vaccaro
Remove the existing FSP 4221.00 headers subdirectory called 4221.00_google, and have Google vendor devices use FSP 4301.01. BUG=b:306181828 TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot skolas to kernel. Change-Id: Ic64b3aec62f0d6302278393bf06d090f43c0d592 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: <srinivas.kulkarni@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-10-18soc/intel/{adl, mtl}: Avoid redundant display init by joining to MBUSSubrata Banik
This patch ensures that the IGD joins the MBUS when the firmware splash screen feature is enabled (aka BMP_LOGO config is enabled). For ChromeOS platform, it prevents the i915 driver from reinitializing the display, which can save up to 75ms-80ms of boot time and eliminate a brief period of blank screen between the firmware splash screen and the OS login prompt. BUG=b:284799726 TEST=Able to build and boot google/rex. Change-Id: I36af167afa902053a987602d494a8830ad9b1b1a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-10-16soc/intel/alderlake: Add config for Client RPL FSP supportBora Guvendik
For Raptor Lake, select Raptor Lake's .fd file and header. TEST=Boot to OS on Google Brya board with RPL silicon. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ib3172b06b23e19be453142af764dd027bfe8043d Reviewed-on: https://review.coreboot.org/c/coreboot/+/78014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-10-11Kconfig: Bring HEAP_SIZE to a common, large valuePatrick Georgi
We have a tiny HEAP_SIZE by default, except when we don't, and mainboards that override it, or not. Since memory isn't exactly at a premium these days, and unused heap doesn't cost anything extra, just crank it up to the highest value we have in the tree by default and remove all overrides. Change-Id: I918a6c58c02496e8074e5fba06e38d9cfd691020 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78270 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-04soc/intel: Select GMA v2 for ADL, MTL, TGL to reflect port/pipe defsSubrata Banik
Intel GFX IP TRANS_DDI_FUNC_CTL register bit definitions have changed since Tiger Lake. This register is used to map ports and pipes to display controllers, so reflecting the correct status is important for detecting physical display end point devices. This patch ensures that ADL, MTL, and TGL SoCs choose GMA version 2 to properly reflect the updated port and pipe register definitions. BUG=b:299137940 TEST=Build and boot google/rex successfully. Change-Id: Ie2082747d18a5f136f410b1019be4d6c801617b1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-04soc/intel: Move USB wake methods to a common ASL fileReka Norman
The ACPI methods for enabling USB wake are identical on ADL, CNL and SKL. Move them to a common ASL file so they can be reused more easily on other SoCs. Also move the USB_PORT_WAKE_ENABLE macro used to create enable bitmasks in devicetree to a common header. BUG=b:300844110 TEST=Use abuild to build kinox, puff, and fizz with and without this change. Check the generated dsdt.aml is unchanged. Change-Id: Iabdfe2bece7fafc284ddf04382f1bbcacc370cce Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-03soc/intel/alderlake: Hook up FSP repo for RPL-P/SMatt DeVillier
Now that Intel has publicly released FSP headers/binaries for RaptorLake-P/S client platforms, set the defaults accordingly if FSP_USE_REPO is not selected. This does not change any existing defaults as the RaptorLake headers in vendorcode are only used when FSP_USE_REPO is not set. TEST=build/boot google/brya (osiris) Change-Id: Ida92d269fcaf6f323599ec174f4dcedbbe65f03c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78190 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-09-28soc/intel/alderlake: Enable LZ4 compression for logo CBFS fileSubrata Banik
This patch selects LZ4 decompression for logo CBFS file. Able to save 2ms of the boot time when HAVE_FSP_LOGO_SUPPORT config is enabled. However, the compressed BMP logo size is increased by ~2KB. Raw BMP Image size is ~97KB. BUG=b:284799726 TEST=Able to see pre-boot splash screen while booting google/redrix with 32MB (W25Q256JWEIM) SPI-Flash. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I98e2c9a4f77d0b91f84eda9aec5060b236bd5e94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78121 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-26soc/intel/alderlake: Move C State Demotion to mainboard configSean Rhodes
Rather than disabling C State demotions for every single Raptor Lake board due to an issue with S0ix, regardless of if they even use S0ix, configure it in the mainboard. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4f941a549bc717ae2f8ec961ead7ac7668347c99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-20soc/intel/alderlake: Hook up the OC watchdogMichał Żygowski
Hook up the OC watchdog common block and initialize it if requested. TEST=Enable watchdog on MSI PRO Z690-A and see the platform resets after some time. Enable the watchdog in driverless mode and see the platform no longer resets and periodic SMI keeps feeding the watchdog. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I1c2c640d48b7e03ad8cd8d6cdf6aac447e93cd86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68945 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-18soc/intel: Update Raptor Lake graphics device IDsBora Guvendik
Added Raptor Lake U graphics device ids. Renamed Raptor Lake U graphics device ids that were marked as Raptor Lake P. Added Raptor Lake P graphics device ids. References: RaptorLake External Design Specification Volume 1 (640555) TEST=Boot to OS Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I44734f927764f872b89e3805a47d16c1ffa28865 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77898 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-16soc/intel/alderlake: Remove ACPI_ADL_IPU_ES_SUPPORTJamie Ryu
DRIVERS_INTEL_MIPI_SUPPORTS_PRE_PRODUCTION_SOC is added to mipi camera driver to extend the same support for all SoCs, so removing this config from Alderlake SoC code. BUG=None TEST=Build rex and brya to check if the build passes without an error. Change-Id: I5bc23fce89f0ae22b64b90cb12621320cac30d85 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2023-09-15vc/intel/raptorlake: Add the FSP v4301.01 headersSean Rhodes
Move the existing FSP 4221.00 headers for Raptor Lake to a subdirectory called 4221.00_google, and select this if the vendor is Google. Add the standard FSP 4301.01 headers to a separate directory, from Intel download #686654, and select this for all other vendors. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Icd99bdee1eeac70dfcaca3d07150d3de6bb83d81 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77101 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-13soc/intel/{tigerlake,alderlake,meteorlake}: Start to unify the TCSS ACPISean Rhodes
The ACPI used for Tiger Lake, Alder Lake and Meteor Lake are very similar, so can be moved to shared code. This commit aligns minor difference between then, such as comments and tabs/spaces. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If6554c7ef9e83740d7ec5dcca6a9d7e32fb182db Reviewed-on: https://review.coreboot.org/c/coreboot/+/77453 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-12cpu/intel: Move is_tme_supported() from soc/intel to cpu/intelJeremy Compostella
It makes the detection of this feature accessible without the CONFIG_SOC_INTEL_COMMON_BLOCK_CPU dependency. BUG=288978352 TEST=compilation Change-Id: I005c4953648ac9a90af23818b251efbfd2c04043 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77697 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-08soc/intel/alderlake_n: Hook up the FSP repositoryFelix Singer
Change-Id: I57b54653bd29a728825210403c8f426eb1c9cc48 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-09-01soc/intel/{adl,jsl,mtl,tgl}: Add ACPI name for GNA deviceMatt DeVillier
Add SA_DEV_SLOT_GNA definition to SoCs missing it, so the name resolves properly. TEST=tested with rest of patch train Change-Id: I31c8b14e5083fc8e212a4e32330125fa72696c73 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: CoolStar <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-21soc/intel/alderlake: add GPIO definitions for RPL PCHTim Crawford
The RPL PCH uses a different ACPI Device ID than ADL PCH. Ref: Intel 700 Series Chipset Family PCH Datasheet, Volume 1 (#743835) Change-Id: I03f47a43ff985213ad617e834db7f974f687d877 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-21vc/intel/fsp2_0: Add a copy of ADL-S IOT FSP MemInfoHob.h for RPL-S IOTMichał Żygowski
Similar situation happened last year when IoT FSP for ADL-S came out before the Client FSP variant: https://github.com/intel/FSP/issues/83 It seems IoT FSP publishes the MemInfoHob.h file much later due to legal reasons. Hack the missing file to get the builds using RPL-S IoT FSP from repo working properly. This change could be merged, subject for later revert (when the header file is published). Change-Id: Iec35db4573a3c3d011e4c1edf1c82a5c34438695 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-21soc/intel/alderlake: Guard PchPcie{Clock,Power}Gating on RPL FSPMichał Żygowski
PchPcieClockGating and PchPciePowerGating UPDs are not yet available in RPL-S IOT FSP. It also looks like those UPDs are not generally available in all public RaptorLake FSP headers yet, so guard it against SOC_INTEL_RAPTORLAKE to avoid build errors. Change-Id: Iedac21bafa3428957e054fc8fefa38f9f776772d Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77337 Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-08-20soc/intel/alderlake_n: Allow using the microcode repoFelix Singer
Allow users of Alderlake N processors to use the microcode repository and also add their related microcode blob to the list of microcodes which should be included in the coreboot rom. Change-Id: I11c9cb13fa81118bfcb819bad5fb39731c7e3e76 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
2023-08-17soc/intel/alderlake: Set PchHdaSdiEnable for Alder LakeSean Rhodes
This UPD does exist for Alder Lake, so set it there also. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If2f405804ab675aaf6dbf8b12d149566055b9eef Reviewed-on: https://review.coreboot.org/c/coreboot/+/77125 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-17soc/intel/alderlake: Add provision to show pre-boot splash screenSubrata Banik
This patch adds the ability to show a pre-boot splash screen on Meteor Lake systems using FSP-S. The patch calls into `fsp_convert_bmp_to_gop_blt()` when the `BMP_LOGO` config is enabled. This function converts a BMP file to a BLT buffer, which is then used by FSP-S to render the splash screen. Additionally, increase the heap size (malloc'able size) upto 512KB (when BMP_LOGO config is enabled) to accommodate high resolution logo file. BUG=b:284799726 TEST=Able to see splash screen while booting google/marasov with BMP_LOGO config enable. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9f4d1bc0aa991e784624ca19ba96a259ab8ddfa6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-16soc/intel/alderlake/chip.h: Use boolean type where applicableMichael Strosche
Change-Id: If26184058536590b70bbb03209913118307ff6c5 Signed-off-by: Michael Strosche <michael.strosche@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76830 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-11soc/intel/alderlake: Remove dummy CPU_SPECIFIC_OPTIONSElyes Haouas
Change-Id: I83574032ef506a411571e8363f476f322ac13e5e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76686 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-11soc/intel/alderlake: Disable PCIe clock gatingPatrick Rudolph
Intel requires that all enabled PCIe PCH ports have a CLK_REQ signal connected. The CLK_REQ is used to wake the silicon when link entered L1 link-state. L1 link-state is also entered on PCI-PM D3, even with ASPM L1 disabled. When no CLK_REQ signal is used, for example when it's using a free running clock the silicon will never wake from L1 link state. This will trigger a MCE. Starting with FSP MR4 the UPD 'PchPcieClockGating' allows to work around this issue by disabling ClockGating. Disabling ClockGating should be avoided as the silicon draws more power when it is idle. TEST: Verified on two boards, one with missing CLK_REQ on a PCH root port, that the code does the right decision to disable UPD PchPcieClockGating and PchPciePowerGating when necessary. Change-Id: I673bbdbadc9afbed6a7bd5ce9f35dc70716d875b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-08-09Revert "soc/intel/{adl, cmn/pcie}: Fix ASPM configuration enum definitions"Jeremy Soller
This reverts commit 5dfec718290609dc0fd0331070ad703107e0b7e7. Reason for revert: This change made it impossible to disable ASPM by FSP parameter. ASPM_DISABLE would result in the FSP parameter not being programmed, causing it to be the FSP default value instead. This additionally fixes MTL to match ADL. Change-Id: I60c0ea08513fcb0035449ea3fef1681de528c545 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75280 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-08ACPI: Add helper fill_fadt_extended_pm_io()Kyösti Mälkki
Once platform code has filled in the (legacy) ACPI PM register map, added function will fill in the extended entries in FADT. TEST=samsung/lumpy and amd/mandolin FADT stays unchanged. Change-Id: I90925fce35458cf5480bfefc7cdddebd41b42058 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-03soc/intel/alderlake/meminit.c: Guard CsPiStartHighinEct properlyMichał Żygowski
Build issue introduced by patch CB:76418 (commit hash 01025d3ae78e02192d389f22abd36747e3d8c63b) for Google boards. Patch has not been rebased to latest master and tested before submission causing the Jenkins jobs to fail. Change-Id: I95bd2485b98be4ab3a39eaaebb9efb34db93bbe8 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76915 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03src/soc/intel/alderlake: add SOC_INTEL_RAPTORLAKE_PCH_S symbolMichał Żygowski
Introduce new symbol SOC_INTEL_RAPTORLAKE_PCH_S that can be selected by board with RPL-S PCH. For now only the IoT variant of RPL-S FSP is available for use with 700 series chipsets. Boards with 600 series chipsets can still use RPL CPUs with the ADL-S C.0.75.10, which contains minimal RPL-S CPU support. Change-Id: I303fac78dac1ed7ccc9d531a6c3c10262f7273ee Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-03soc/intel/alderlake: Depend RPL-guarded FSP UPDs on FSP_USE_REPOMichał Żygowski
Only the headers on Intel FSP repository have the CnviWifiCore present. Options guarded for RPL like: DisableDynamicTccoldHandshake or EnableFastVmode and IccLimit is also supported by all public FSPs (except ADL-N for the handshake). Options like LowerBasicMemTestSize and DisableSagvReorder have to be guarded when FSP_USE_REPO is not selected, as publci FSPs do not have these options. Use FSP_USE_REPO instead of/in addition to SOC_INTEL_RAPTORLAKE as dependency on the guarded UPDs to make them available for FSPs that support them as well. Also prioritize the headers from FSP repo over vendorcode headers if FSP_USE_REPO is selected. Change-Id: Id5a2da463a74f4ac80dcb407a39fc45b0b6a10a8 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
2023-07-31soc/intel/alderlake: Allow channel 0 for DDR5 memory-downJeremy Soller
This matches the change done for DDR4 in commit 8509c25eece8 ("soc/intel/alderlake: Allow channel 0 for memory-down"). Fixes detection of the on-board RAM (Samsung M425R1GB4BB0-CQKOD) on the System76 Lemur Pro 12 (Clevo L140AU). The Clevo L140*U are the only boards in the tree using mixed memory topology. Change-Id: I395f898472a9a8f857fd6b0564b95c787b96080b Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-07-31soc/intel/alderlake/hsphy.c: Use C99 flexible arraysElyes Haouas
Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: Id0baf970dbe94a8ebf75f8dbabc6abe345d1c454 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-07-21soc/intel/alderlake: Hook up UPD PchHdaSdiEnableBora Guvendik
Hook the PchHdaSdiEnable UPD so that mainboard can change the settings via devicetree. PchHdaSdiEnable UPD enable HDA SDI lanes. BUG=b:268546941 TEST=Verified the settings on google/brya using debug FSP logs. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I82bbfa5442936aefa53f8826e395b7ce75c895a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-07-19soc/intel/alderlake: Use 1MB CBMEM console buffer with FSP debugSubrata Banik
Patch to increase CONSOLE_CBMEM_BUFFER_SIZE to contain FSP debug serial log. The existing implementation uses larger cbmem size irrespective of FSP debug is enabled or not. Ideally. larger cbmem size is required only if FSP debug is enabled. Bug=b:284124701 TEST=Able to build and boot google/marasov. Change-Id: I9a9e660f2738813808e0dd65d2783424b49f9a5e Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-19soc/intel/{adl, mtl}: Reduce CAR usage while using FSP debug binariesSubrata Banik
Reduces the CAR (Cache-as-RAM) variable usage while using FSP debug binaries, which can prevent the CAR from becoming too full and unable to integrate other CAR global variables. This change has the following downsides: - FSP debug output into the cbmem buffer will be partial. To test this change, you can: Build and boot google/rex without any function impact with non-serial and serial FSP debug image (unless what has been documented here). Bug=b:284124701 TEST=Able to build and boot google/rex. Change-Id: I16a1aa25fd32327d03a37381a696c86c95014ba0 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-07-18soc/intel/alderlake: Hook up CsPiStartHighinEct UPDKane Chen
This commit provides option for board to set CsPiStartHighinEct FSP UPD using a new cs_pi_start_high_in_ect mb_cfg field. BUG=b:279835630 BRANCH=none TEST=CsPiStartHighinEct UPD is set properly Change-Id: I7d0d5f3c782e29fb047ea421e1a5fdfc30bcc26d Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-17soc/intel/adl: Add power limits for RPL-H 4P+8E 45WTim Crawford
Change-Id: I01ae5a484287d2adb1516e1e4551b185b895fdde Ref: RPL-UPH and RPL-U Refresh Platform Design Guide (#686872, rev 2.1) Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-14soc/intel/adl: Add Raptor Lake-HX definitionsTim Crawford
Tested by booting System76 Adder WS 3 (addw3) and Serval WS 13 (serw13) to edk2 payload and then OS. Ref: Intel Raptor Lake EDS, Volume 1 (#640555, rev. 2.8) Change-Id: I6098e9121a3afc4160c8a0c96d597e88095fd65d Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-13soc/intel: Rename pcr.asl to pch_pcr.aslSubrata Banik
The PCR (Private Configuration Register) is applicable to access the P2SB register space starting with the Intel SkyLake generation of SoC. Prior to Intel Meteor Lake SoC generation, the only P2SB existed inside the PCH die. Starting with Meteor Lake SoC, there are two P2SB, one in SoC die (same as PCH die for U/H SoC) and another in IOE die. This patch renames pcr.asl to pch_pcr.asl to reflect the actual source of the P2SB IP in the die (i.e., SoC die or PCH die). BUG=b:290856936 TEST=Able to build and boot google/rex. Change-Id: Idb66293eaab01e1d4bcd4e9482157575fb0adf04 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76407 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-13soc/intel/alderlake: Disable hwp scalibility trackingBora Guvendik
Disable scalability tracking for autonomous frequency control in order to improve power and performance. BUG=b:280021171 TEST=Boot to OS on brya0 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: If71ee5374c67611b32691bbec4effdf828b3e566 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74723 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-07-13soc/intel/alderlake: Hook up UPD EnableHwpScalabilityTrackingBora Guvendik
Hook the newly exposed EnableHwpScalabilityTracking UPD up so that boards can configure is via devicetree. BUG=b:280021171 TEST=Verified by enabling/disabling the UPD on google/brya Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I4c8845c445d46caa30a0245386ab9cd690d2623f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74722 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-07-13soc/intel/alderlake: Hook up UPD DisableSagvReorderBora Guvendik
Hook the newly exposed DisableSagvReorder UPD up so that boards can configure is via devicetree. BUG=b:268546941 TEST=Verified by enabling/disabling the UPD on google/brya Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I89235d9384b67f03e68425aadd3458e1c77ff555 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-07-13soc/intel/alderlake: Disable SaGV reorderingBora Guvendik
Disable re-ordering SaGv point on warm reset so that most performant SaGv point is picked after memory training and boot time is reduced. BUG=b:268546941 TEST=Observe boot time improvement with these two UPDs set Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I44a1c054d52bb8585a320bb8a52a8f137e639804 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74721 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-13soc/intel/alderlake: Reduce memory test sizeBora Guvendik
Enable upd to reduce size of the memory test. BUG=b:268546941 TEST=Observe boot time improvement with these two UPDs set Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I95c7d8503596c2712d7abe123ed1f911ac4abacf Reviewed-on: https://review.coreboot.org/c/coreboot/+/74719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-13soc/intel/alderlake: Hook up UPD LowerBasicMemTestSizeBora Guvendik
Hook the newly exposed LowerBasicMemTestSize UPD up so that boards can configure is via devicetree. BUG=b:268546941 TEST=Verified by enabling/disabling the UPD on google/brya Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ib813e9f3b7419a3cb54b4e176dcc5cc74a783dfd Reviewed-on: https://review.coreboot.org/c/coreboot/+/74718 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-07-12soc/intel: Replace number in RPL-S ESPI PCI IDs by chipset nameMichał Żygowski
Change-Id: I68416e1633c3d67070790a9db2cd9a13a8981042 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-12soc/intel: Fix W790 chipset nameMichał Żygowski
In newer ADL/RPL PCH EDS 619362 revision 2.1 the ESPI ID 0x7A8A belongs to the W790 chipset. Earlier revisions had the chipset with ID 0x7A8A named W685, which was probably just a temporary name. Change the naming throughout the tree to W790, which is the real existing chipset. Change-Id: I87603298d655e9bf898b34acdd5b403f5affaee3 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2023-07-12treewide: Drop the suffixes from ADL and RPL CPUID macros and stringsMichał Żygowski
CPUID is the same for Alder Lake and Raptor Lake S and HX variants. To reduce the confusion and concerns how to name the macros, remove the suffixes from macros and platform reporting strings. Thankfully the stepping names are unique across mobile (P suffixed) and desktop (S and HX suffixed) SKUs. Distinguishing the S from HX is possible via host bridge PCI ID. Change-Id: Ib08fb0923481541dd6f358cf60da44d90bd75ae2 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>