diff options
| author | Bora Guvendik <bora.guvendik@intel.com> | 2023-04-24 18:22:55 -0700 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2023-07-13 01:06:09 +0000 |
| commit | 3708f54bb58c9d7a61884cd263f4dfa569e5a14c (patch) | |
| tree | f710468c0f17f655940eb67ad32a23b3654699a5 /src/soc/intel/alderlake | |
| parent | 6e64c01d08a56b30c970d6a86466dc8dfb06d17e (diff) | |
soc/intel/alderlake: Disable hwp scalibility tracking
Disable scalability tracking for autonomous frequency control in
order to improve power and performance.
BUG=b:280021171
TEST=Boot to OS on brya0
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: If71ee5374c67611b32691bbec4effdf828b3e566
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74723
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/soc/intel/alderlake')
| -rw-r--r-- | src/soc/intel/alderlake/chipset.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index 5d717b8e54..0ab7c8a87a 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -96,6 +96,9 @@ chip soc/intel/alderlake # Disable SaGV reordering operation to start with SaGV point 4 and reduce boot time. register "disable_sagv_reorder" = "true" + # Disable hwp scalability tracking. + register "enable_hwp_scalability_tracking" = "false" + # NOTE: if any variant wants to override this value, use the same format # as register "common_soc_config.pch_thermal_trip" = "value", instead of # putting it under register "common_soc_config" in overridetree.cb file. |