diff options
| author | Sowmya Aralguppe <sowmya.aralguppe@intel.com> | 2024-06-18 06:41:06 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-07-12 18:37:54 +0000 |
| commit | 702902d71fae63fd35362c82f2a369b42af1a77f (patch) | |
| tree | 23e7b94bffeab78976e75ac11dde19524ded65e1 /src/soc/intel/alderlake | |
| parent | c0871f62f74f776d961da219eab16bcc3235cfda (diff) | |
soc/intel: Adapt crashlog IP to also support 64-bit
This patch extends the crashlog IP support beyond 32-bit mode to
support Intel future generation SoCs, which may require crashlog
support for 64-bit architectures. uintptr_t data type is used for
Address pointers and void* for dereferencing
BUG=b:346676856
TEST=Successfully built Meteor Lake (rex) and tested for google/rex0
and google/rex64 images.
Change-Id: I552257d3770abb409e2dcd8a13392506b5e7feb7
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83106
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/alderlake')
| -rw-r--r-- | src/soc/intel/alderlake/crashlog.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/src/soc/intel/alderlake/crashlog.c b/src/soc/intel/alderlake/crashlog.c index 5a08c25a62..a85fa0144a 100644 --- a/src/soc/intel/alderlake/crashlog.c +++ b/src/soc/intel/alderlake/crashlog.c @@ -23,7 +23,7 @@ static pmc_crashlog_desc_table_t descriptor_table; static tel_crashlog_devsc_cap_t cpu_cl_devsc_cap; static cpu_crashlog_discovery_table_t cpu_cl_disc_tab; -u32 __weak cl_get_cpu_mb_int_addr(void) +uintptr_t __weak cl_get_cpu_mb_int_addr(void) { return CRASHLOG_MAILBOX_INTF_ADDRESS; } @@ -119,7 +119,7 @@ bool pmc_cl_discovery(void) return true; } -u32 cl_get_cpu_bar_addr(void) +uintptr_t cl_get_cpu_bar_addr(void) { u32 base_addr = 0; if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR0) { @@ -137,7 +137,7 @@ u32 cl_get_cpu_bar_addr(void) } -u32 cl_get_cpu_tmp_bar(void) +uintptr_t cl_get_cpu_tmp_bar(void) { return sram_get_bar(); } @@ -189,8 +189,12 @@ static bool cpu_cl_get_capability(tel_crashlog_devsc_cap_t *cl_devsc_cap) static bool cpu_cl_gen_discovery_table(void) { - u32 bar_addr = 0, disc_tab_addr = 0; + uintptr_t bar_addr = 0, disc_tab_addr = 0; bar_addr = cl_get_cpu_bar_addr(); + + if (!bar_addr) + return false; + disc_tab_addr = bar_addr + cpu_cl_devsc_cap.discovery_data.fields.discovery_table_offset; memset(&cpu_cl_disc_tab, 0, sizeof(cpu_crashlog_discovery_table_t)); |