| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2024-09-04 | soc/intel: Refactor ITSS macros | Subrata Banik | |
| This patch refactors ITSS related SoC specific macros by consolidating them into a common itss.h file. This improves code maintainability and reduces redundancy as each SoC previously defined the same macros. Specific changes include: - Move SoC specific ITSS macros into intelblocks/itss.h. - SoC code now includes intelblocks/itss.h instead of the SoC-local soc/itss.h. - Drop soc/itss.h from static ASL files. - Delete soc/itss.h from all SoC locals except Apollo Lake and Sky Lake. TEST=Able to build and boot google/hatch, google/xol and google/karis. Change-Id: I6461dc93b0d21bec5429075bc26435bae3754d74 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84183 Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> | |||
| 2024-08-15 | soc/intel/alderlake: Correct ISH partition availability check | Subrata Banik | |
| The previous implementation incorrectly assumed that the presence of a UFS device implied the availability of the ISH partition. This is not always true, especially on Alder Lake platforms where ISH may be enabled by default even without UFS. This patch fixes the issue by directly checking for the presence of the ISH device to determine if the ISH partition is available. BUG=b:359440547 TEST=1. Able to dump the ISH version with UFS device: ``` tirwen-rev3 ~ # cbmem -c -1 | grep ISH [DEBUG] ISH version: 5.4.2.7780 ``` 2. Able to dump the ISH version with eMMC device: ``` trulo-rev1 ~ # cbmem -c | grep ISH [DEBUG] ISH version: 5.4.2.7780 ``` Change-Id: I411e36606c0697f91050af40e0636f7c64810e95 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com> | |||
| 2024-01-31 | include/device/device.h: Remove CHIP_NAME() macro | Nicholas Sudsgaard | |
| Macros can be confusing on their own; hiding commas make things worse. This can sometimes be downright misleading. A "good" example would be the code in soc/intel/xeon_sp/spr/chip.c: CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev, This appears as CHIP_NAME() being some struct when in fact these are defining 2 separate members of the same struct. It was decided to remove this macro altogether, as it does not do anything special and incurs a maintenance burden. Change-Id: Iaed6dfb144bddcf5c43634b0c955c19afce388f0 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80239 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | |||
| 2023-10-20 | device/device.h: Rename pci_domain_scan_bus | Arthur Heymans | |
| On all targets the domain works as a host bridge. Xeon-sp code intends to feature multiple host bridges below a domain, hence rename the function to pci_host_bridge_scan_bus. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I4e65fdbaf0b42c5f4f62297a60d818d299d76f73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78326 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com> | |||
| 2023-09-01 | soc/intel/{adl,jsl,mtl,tgl}: Add ACPI name for GNA device | Matt DeVillier | |
| Add SA_DEV_SLOT_GNA definition to SoCs missing it, so the name resolves properly. TEST=tested with rest of patch train Change-Id: I31c8b14e5083fc8e212a4e32330125fa72696c73 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: CoolStar <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> | |||
| 2023-06-15 | {driver, mb, soc}: Rename Intel CSE FPT config to ISH FW version config | Subrata Banik | |
| This patch renames `SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION` config to `SOC_INTEL_STORE_ISH_FW_VERSION` to ensure the usage of this config is clear. Any platform would like to fetch the currently running ISH firmware version should select this configuration. TEST=Able to build and boot google/marasov. Change-Id: Ie503d6a5bf5bd0d3d561355b592e75b22c910bf5 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75767 Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> | |||
| 2023-04-22 | soc/intel/alderlake: Implement `soc_is_ish_partition_enabled` override | Subrata Banik | |
| This patch implements `soc_is_ish_partition_enabled()` override to uniquely identify the SKU type between UFS and non-UFS to conclude if ISH partition is enabled and need to retrieve the ISH version from CSE FPT by sending HECI command. TEST=Able to uniquely identify the UFS and non-UFS SKUs while booting to google/marasov. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7771aebb988f11d9d1b2824aa28e6f294fd67c25 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74532 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> | |||
| 2023-04-11 | soc/intel/alderlake: Hook up P2SB PCI ops | Michał Żygowski | |
| P2SB device is being hidden from coreboot by FSP-S. This breaks the resource allocator which does not report P2SB BAR via intel common block P2SB driver. Hook up the common block P2SB driver ops to soc_enable function so that the resources will be reported. The P2SB device must be set as hidden in the devicetree. This fixes the silent resource allocation conflicts on machines with devices having big BARs which accidentally overlapped P2SB BAR. TEST=Boot MSI PRO Z690-A with multiple PCIe devices/dGPUs with big BARs and see resource conflicts no longer occur. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I7c59441268676a8aab075abbc036e651b9426057 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> | |||
| 2023-04-11 | soc/intel/{adl, cmn}: Send CSE EOP Async CMD early | Subrata Banik | |
| This patch sends the CSE EOP command asynchronous implementation early as part of `soc_init_pre_device`. Without this patch the duration between asynchronous CSE EOP send and receive commands is not ample whichcauses idle delay while waiting for EOP response. The goal of the CSE async implementation is to avoid idle delay while capturing the response from CSE EOP cmd. This patch helps to create ample duration between CSE EOP command being sent and response being captured. TEST=Able to boot google/marasov EVT sku to ChromeOS and observed ~30ms of boot time savings (across warm and cold reset scenarios). Without this patch: 963:returning from FspMultiPhaseSiInit 907,326 (97,293) ... ... 115:finished elog init 967,343 (2,581) 942:before sending EOP to ME 967,821 (478) … 16:finished LZMA decompress (ignore for x86) 1,017,937 (12,135) 943:after sending EOP to ME 1,067,799 (49,861) … … 1101:jumping to kernel 1,144,587 (13,734) Total Time: 1,144,549 With this patch: 963:returning from FspMultiPhaseSiInit 918,291 (97,320) 942:before sending EOP to ME 918,522 (230) ... ... 16:finished LZMA decompress (ignore for x86) 1,029,476 (12,483) 943:after sending EOP to ME 1,033,456 (3,980) ... ... 1101:jumping to kernel 1,111,410 (14,007) Total Time: 1,111,375 Change-Id: Idaf45ef28747bebc02347f0faa77cc858a4a8ef1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> | |||
| 2023-02-13 | soc/intel/alderlake: Fix ACPI name for DPTF | CoolStar | |
| The correct ACPI device for DPTM is TCPU; fixing this puts the participant devices under the correct parent device, and allows Windows to properly go into S0ix. TEST=builb/boot Win11 on google/banshee, verify Si0x functional. Change-Id: I1b3e2655d4d42e008dead9bc87b73ce02868fdfa Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> | |||
| 2022-12-27 | soc/intel/alderlake: Use common gpio.h include | Dinesh Gehlot | |
| Replace the intelblocks/gpio.h and soc/gpio.h includes with the common gpio.h which will include soc/gpio.h which will include intelblocks/gpio.h BUG=b:261778357 TEST=Able to build and boot Google/brya. Change-Id: Ia90a8ea7b4ee125657c7277e3e14018cfe5423a9 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71266 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> | |||
| 2022-08-24 | soc/intel/alderlake/hsphy: Add support for HSPHY firmware loading | Michał Żygowski | |
| BIOS must send the IP_LOAD HECI command to fetch the firmware for CPU PCIe Gen5 and upload it via CPU REG BAR prior FSP Silicon Init. Implementation based on public Slimbootloader's "Silicon/AlderlakePkg/Library/CpuPcieHsPhyInitLib". TEST=Boot MSI PRO Z690-A and see the HSPHY FW is loaded. PCIe x16 Gen3 GPU card started working in the PCIE 5.0 slot. [DEBUG] HECI: Sending Get IP firmware command [DEBUG] HECI: Get IP firmware success. Response: [DEBUG] Payload size = 0x6944 [DEBUG] Hash type used for signing payload = 0x3 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I6c6c11581e3d3d9bab0131fae6ef487cafe98080 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> | |||
| 2022-06-28 | soc/alderlake: Add ADL-S PCIe support | Michał Żygowski | |
| Extend the code to support ADL-S PCIe Root Ports. Based on DOC #619362 and #619501. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ibb57ad5b11684c0079e384d9a6ba5c10905c1a23 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63654 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> | |||
| 2022-06-20 | soc/intel/alderlake/chip.c: Add missing ADL-S USB ports ACPI names | Michał Żygowski | |
| ADL-S has more USB ports than mobile chipsets. Add missing ACPI names. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ice5f7784f9de0364681be00fc5cc445caf9d1b3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/63655 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> | |||
| 2022-05-16 | soc/intel/*: Use SSDT to pass A4GB and A4GS | Arthur Heymans | |
| GNVS is more fragile as you need to keep struct elements in sync with ASL code. Change-Id: I2cd5e6b56e4a0dbbb11f4a0ac97e8f84d53b90ec Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> | |||
| 2022-05-06 | soc/intel/alderlake: Add missing ACPI device path names | Tarun Tuli | |
| A few ACPI device path name handlers are missing. Add handling to ensure that these names are returned during acpi_device_path() calls. TEST=Built and tested on brya Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I37d6dd5df921c931af72dd469c3f4067c61b0df3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> | |||
| 2022-03-10 | soc/intel/adl: Send EOP early in the boot sequence | MAULIK V VAGHELA | |
| As part of boot time optimization, one of the culprit was CSE where response to End Of Post (EOP) command used to take ~60ms. Earlier patch was pushed to delay the EOP to reduce response time to ~5-7 ms. During this stage overall platform boot time was ~1.15 seconds. Once boot time was optimized to ~ 1 seconds, CSE EOP time again increased to ~80 ms since coreboot used to send EOP at the time where CSE was busy. This created some back and forth moving of sending EOP command function within coreboot sequence. Upon debugging using traces, it was found that coreboot used to send EOP late where CSE was busy loading other IP payload, so it might take more time to respond. In order to avoid delayed response, coreboot has to send EOP in stage when CSE is done with firmware init and it will be ready to serve EOP as soon as possible. This also aligns with previous flow where FSP used to send EOP once silicon init is done and coreboot used to rely on FSP to send this message. Moving EOP to earlier stage (From SoC) meets the requirement and CSE EOP time reduces from ~60 ms to ~20 ms on Brya board. Note that once SoC code sends EOP, coreboot common code won't send it again since common code already has check in case EOP is sent earlier. BUG=b:211085685 BRANCH=firmware-brya-14505.B TEST=Tested on Brya system before and after the changes. Observed ~40ms savings in boot time. Change-Id: I9401d5e36ad43cdc0dfe947aabc82528d824df9b Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> | |||
| 2022-02-21 | soc/intel/alderlake: Enable eMMC based on dev enabled | Krishna Prasad Bhat | |
| 1. Add eMMC device function in pci_devs.h. 2. Enable eMMC device and configuration based on dev enabled. 3. Add SOC acpi name for eMMC. Change-Id: I44f17420f7a2a1ca0fbb6cfb1886b1617c5a5064 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> | |||
| 2022-02-07 | treewide: Remove "ERROR: "/"WARN: " prefixes from log messages | Julius Werner | |
| Now that the console system itself will clearly differentiate loglevels, it is no longer necessary to explicitly add "ERROR: " in front of every BIOS_ERR message to help it stand out more (and allow automated tooling to grep for it). Removing all these extra .rodata characters should save us a nice little amount of binary size. This patch was created by running find src/ -type f -exec perl -0777 -pi -e 's/printk\(\s*BIOS_ERR,\s*"ERROR: /printk\(BIOS_ERR, "/gi' '{}' ';' and doing some cursory review/cleanup on the result. Then doing the same thing for BIOS_WARN with 's/printk\(\s*BIOS_WARNING,\s*"WARN(ING)?: /printk\(BIOS_WARNING, "/gi' Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I3d0573acb23d2df53db6813cb1a5fc31b5357db8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Lance Zhao Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> | |||
| 2022-01-31 | soc/intel/adl: Update devicetree based on remapping for TBT PCIe | MAULIK V VAGHELA | |
| ADL has 4 TBT root ports which are PCIe compliant. TBT uses PCIe coalescing logic where in case root port 0 is disabled, other enabled root port is remapped to port 0. coreboot handles this remapping scenarios for PCH and CPU PCIe root ports and not for TBT root ports. This patch uses the same function used for PCIe remapping to update devicetree based on coalescing and SoC needs to pass correct function number and number of slots. BUG=b:210933428 BRANCH=None TEST=Check if TBT remapping happens correctly and ACPI tables are generated correctly. Change-Id: Ied16191d6af41f8e2b31baee80cb475e7d557010 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> | |||
| 2022-01-06 | soc/intel/alderlake: Add minimal ACPI support for PEG ports | Tim Wawrzynczak | |
| Add minimal Device entries with just an _ADR for each of the PEG ports for P and M chipsets (N does not have any PEG ports). Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Id1009004969729eddf7005fa190f5e1ca2d7b468 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> | |||
| 2021-09-16 | soc/intel/alderlake: Add igd device | Wisley Chen | |
| Add igd device name in soc_acpi_name(), and src/drivers/gfx/generic can generate device in GFX0 scope in ssdt. BUG=b:198188272 TEST=emerge-brya coreboot and check ssdt. Change-Id: Id0c50254a8a25b47368e932c99243f4f02250b82 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> | |||
| 2021-07-20 | soc/intel/alderlake: Add support for I2C6 and I2C7 | Varshit B Pandya | |
| As per the EDS revision 1.3 add support for I2C6 and I2C7. Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: Id918d55e48b91993af9de8381995917aef55edc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55996 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> | |||
| 2021-06-29 | soc/intel/alderlake: Enable support for common IRQ block | Tim Wawrzynczak | |
| Since GPIO IO-APIC IRQs are fixed in hardware (RO registers), this patch allows ADL boards to dynamically assign PCI IRQs. This means not relying on FSP defaults, which eliminates the problem of PCI IRQs interfering with GPIO IRQs routed to the same IRQ, when both have selected IO-APIC routing. BUG=b:176858827 TEST=brya0, grep 'IO-APIC' /proc/interrupts (compressed to fit) 0: 36 0 0 0 0 0 0 0 IO-APIC 2-edge time 1: 0 0 9 0 0 0 0 0 IO-APIC 1-edge i804 8: 0 0 0 0 0 0 0 0 IO-APIC 8-edge rtc0 9: 0 21705 0 0 0 0 0 0 IO-APIC 9-fasteoi acpi 14: 0 0 0 0 0 0 0 0 IO-APIC 14-fasteoi INTC 18: 0 0 0 0 0 0 0 0 IO-APIC 18-fasteoi inte 20: 0 0 0 0 0 0 0 394 IO-APIC 20-fasteoi idma 23: 2280 0 0 0 0 0 0 0 IO-APIC 23-fasteoi idma 26: 0 0 26 0 0 0 0 0 IO-APIC 26-fasteoi idma 27: 0 0 0 6 0 0 0 0 IO-APIC 27-fasteoi idma 28: 0 0 0 0 0 0 0 0 IO-APIC 28-fasteoi idma 29: 0 0 0 0 25784 0 0 0 IO-APIC 29-fasteoi idma 30: 0 0 0 0 0 0 0 0 IO-APIC 30-fasteoi idma 31: 0 0 0 0 0 0 226 0 IO-APIC 31-fasteoi idma 77: 0 0 0 0 0 2604 0 0 IO-APIC 77-edge cr50 100: 0 0 0 0 0 0 0 0 IO-APIC 100-fasteoi ELAN 103: 0 0 0 0 0 0 0 0 IO-APIC 103-fasteoi chro abbreviated _PRT dump: If (PICM) Package (){0x0002FFFF, 0, 0, 0x10}, Package (){0x0004FFFF, 0, 0, 0x11}, Package (){0x0005FFFF, 0, 0, 0x12}, Package (){0x0006FFFF, 0, 0, 0x13}, Package (){0x0006FFFF, 1, 0, 0x14}, Package (){0x0007FFFF, 0, 0, 0x15}, Package (){0x0007FFFF, 1, 0, 0x16}, Package (){0x0007FFFF, 2, 0, 0x17}, Package (){0x0007FFFF, 3, 0, 0x10}, Package (){0x000DFFFF, 0, 0, 0x11}, Package (){0x0012FFFF, 0, 0, 0x18}, Package (){0x0012FFFF, 1, 0, 0x19}, Package (){0x0014FFFF, 0, 0, 0x12}, Package (){0x0014FFFF, 1, 0, 0x13}, Package (){0x0015FFFF, 0, 0, 0x1A}, Package (){0x0015FFFF, 1, 0, 0x1B}, Package (){0x0015FFFF, 2, 0, 0x1C}, Package (){0x0015FFFF, 3, 0, 0x1D}, Package (){0x0016FFFF, 0, 0, 0x14}, Package (){0x0016FFFF, 1, 0, 0x15}, Package (){0x0016FFFF, 2, 0, 0x16}, Package (){0x0016FFFF, 3, 0, 0x17}, Package (){0x0017FFFF, 0, 0, 0x10}, Package (){0x0019FFFF, 0, 0, 0x1E}, Package (){0x0019FFFF, 1, 0, 0x1F}, Package (){0x0019FFFF, 2, 0, 0x20}, Package (){0x001CFFFF, 0, 0, 0x10}, Package (){0x001CFFFF, 1, 0, 0x11}, Package (){0x001CFFFF, 2, 0, 0x12}, Package (){0x001CFFFF, 3, 0, 0x13}, Package (){0x001DFFFF, 0, 0, 0x10}, Package (){0x001DFFFF, 1, 0, 0x11}, Package (){0x001DFFFF, 2, 0, 0x12}, Package (){0x001DFFFF, 3, 0, 0x13}, Package (){0x001EFFFF, 0, 0, 0x14}, Package (){0x001EFFFF, 1, 0, 0x15}, Package (){0x001EFFFF, 2, 0, 0x16}, Package (){0x001EFFFF, 3, 0, 0x17}, Package (){0x001FFFFF, 1, 0, 0x15}, Package (){0x001FFFFF, 2, 0, 0x16}, Package (){0x001FFFFF, 3, 0, 0x17}, Package (){0x001FFFFF, 0, 0, 0x14}, Else Package (){0x0002FFFF, 0, 0, 0x0B}, Package (){0x0004FFFF, 0, 0, 0x0A}, Package (){0x0005FFFF, 0, 0, 0x0B}, Package (){0x0006FFFF, 0, 0, 0x0B}, Package (){0x0006FFFF, 1, 0, 0x0B}, Package (){0x0007FFFF, 0, 0, 0x0B}, Package (){0x0007FFFF, 1, 0, 0x0B}, Package (){0x0007FFFF, 2, 0, 0x0B}, Package (){0x0007FFFF, 3, 0, 0x0B}, Package (){0x000DFFFF, 0, 0, 0x0A}, Package (){0x0014FFFF, 0, 0, 0x0B}, Package (){0x0014FFFF, 1, 0, 0x0B}, Package (){0x0016FFFF, 0, 0, 0x0B}, Package (){0x0016FFFF, 1, 0, 0x0B}, Package (){0x0016FFFF, 2, 0, 0x0B}, Package (){0x0016FFFF, 3, 0, 0x0B}, Package (){0x0017FFFF, 0, 0, 0x0B}, Package (){0x001CFFFF, 0, 0, 0x0B}, Package (){0x001CFFFF, 1, 0, 0x0A}, Package (){0x001CFFFF, 2, 0, 0x0B}, Package (){0x001CFFFF, 3, 0, 0x0B}, Package (){0x001DFFFF, 0, 0, 0x0B}, Package (){0x001DFFFF, 1, 0, 0x0A}, Package (){0x001DFFFF, 2, 0, 0x0B}, Package (){0x001DFFFF, 3, 0, 0x0B}, Package (){0x001EFFFF, 0, 0, 0x0B}, Package (){0x001EFFFF, 1, 0, 0x0B}, Package (){0x001EFFFF, 2, 0, 0x0B}, Package (){0x001EFFFF, 3, 0, 0x0B}, Package (){0x001FFFFF, 1, 0, 0x0B}, Package (){0x001FFFFF, 2, 0, 0x0B}, Package (){0x001FFFFF, 3, 0, 0x0B}, Package (){0x001FFFFF, 0, 0, 0x0B}, dmesg shows no GSI or PCI errors, TPM & touchpad IRQs still work Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I1e7a708183ac4170b28da9565137fa2f5088a7eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/54683 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> | |||
| 2021-04-21 | soc/intel: Replace open-coded buffer length calculation | Angel Pons | |
| Use `sizeof(value)` instead of manually calculating the buffer size. Change-Id: Ibe49e40b1c4f2c0b661d94e59059a95bdb204197 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> | |||
| 2021-03-27 | soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.h | Subrata Banik | |
| Lists of changes: 1. Rename MISCCFG_ENABLE_GPIO_PM_CONFIG -> MISCCFG_GPIO_PM_CONFIG_BITS 2. Move MISCCFG_GPIO_PM_CONFIG_BITS definition from intelblock/gpio.h to soc/gpio.h. Refer to detailed description below to understand the motivation behind this change. An advanced GPIO PM capabilities has been introduced since CNP PCH, refer to 'include/intelblock/gpio.h' for detailed GPIO PM bit definitions. Now with TGP PCH, additional bits are defined in the MISCCFG register for GPIO PM control. This results in different SoCs supporting different number of bits. The bits defined in earlier platforms (CNL, CML, ICL) are present on TGL, JSL and ADL too. Hence, refactor the common GPIO code to keep the bit definitions in intelblock/gpio.h, but the definition of MISCCFG_GPIO_PM_CONFIG_BITS is moved to soc/gpio.h so that each SoC can provide this as per hardware support. TEST=On ADL, TGL and JSL platform. Without this CL : GPIO COMM 0 MISCCFG:0xC0 (Bit 6 and 7 enable) With this CL : GPIO COMM 0 MISCCFG: 0x00 (Bit 6 and 7 disable) Change-Id: Ie027cbd7b99b39752941384339a34f8995c10c94 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> | |||
| 2021-02-24 | soc/intel/{adl,jsl,ehl,tgl}: Remove ITSS polarity restore | Aamir Bohra | |
| Post boot SAI PCR access to ITSS polarity regsiter is locked. Restore of ITSS polarity does not take effect anyways. Hence removing the related programming. Change-Id: I1adab45ee903b9d9c1d98a060143445c0cee0968 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> | |||
| 2021-02-09 | soc/amd,intel: Drop s3_resume parameter on FSP-S functions | Kyösti Mälkki | |
| ACPI S3 is a global state and it is no longer needed to pass it as a parameter. Change-Id: Id0639a47ea65c210b9a79e6ca89cee819e7769b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> | |||
| 2021-01-18 | soc/intel/alderlake: Update PCH and CPU PCIe RP table | Eric Lai | |
| According ADL EDS to update the PCH and CPU PCIe RP table. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Idcc21d8028f51a221d639440db4cf5a4e095c632 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> | |||
| 2020-12-30 | soc/intel: hook up new gpio device in the soc chips | Michael Niewöhner | |
| This change adds the required gpio operations struct to soc/common gpio code and hooks them up in all socs currently using the gpio block code, except DNV-NS, which is handled in a separate change. Also, add the gpio device to existing chipset devicetrees. Successfully tested on Supermicro X11SSM-F with CB:48097, X11SSH-TF with CB:48711 and OCP DeltaLake with CB:48672. Change-Id: I81dbbf5397b28ffa7537465c53332779245b39f6 Tested-by: Johnny Lin <Johnny_Lin@wiwynn.com> Tested-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48583 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> | |||
| 2020-10-03 | soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage | Subrata Banik | |
| List of changes: 1. Add required SoC programming till ramstage 2. Include only required headers into include/soc 3. Add CPU, PCH and SA EDS document number and chapter number 4. Fill required FSP-S UPD to call FSP-S API Change-Id: I3394f585d66b14ece67cde9e45ffa1177406f35f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> | |||
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