diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-12-16 15:01:44 -0700 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-01-06 16:49:51 +0000 |
| commit | cf39336ccfcc363162395bddf65113900aaf19fe (patch) | |
| tree | d4d35b0cc16208df4a163606c6a88dbe08586f39 /src/soc/intel/alderlake/chip.c | |
| parent | 40c9c8aa8021348e0fd6916b0e06f21398fb42c9 (diff) | |
soc/intel/alderlake: Add minimal ACPI support for PEG ports
Add minimal Device entries with just an _ADR for each of the PEG ports
for P and M chipsets (N does not have any PEG ports).
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Id1009004969729eddf7005fa190f5e1ca2d7b468
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/soc/intel/alderlake/chip.c')
| -rw-r--r-- | src/soc/intel/alderlake/chip.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index ae28d18815..1fa78fbcd9 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -61,6 +61,9 @@ const char *soc_acpi_name(const struct device *dev) switch (dev->path.pci.devfn) { case SA_DEVFN_ROOT: return "MCHC"; + case SA_DEVFN_CPU_PCIE1_0: return "PEG2"; + case SA_DEVFN_CPU_PCIE6_0: return "PEG0"; + case SA_DEVFN_CPU_PCIE6_2: return "PEG1"; case SA_DEVFN_IGD: return "GFX0"; case SA_DEVFN_TCSS_XHCI: return "TXHC"; case SA_DEVFN_TCSS_XDCI: return "TXDC"; |