diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-05-09 14:33:15 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2022-05-16 06:53:46 +0000 |
| commit | 08769c6d1404c1be0333273d8b988544750ce87d (patch) | |
| tree | ef37aeb920efea81b84ecf50c2ab990c09541b30 /src/soc/intel/alderlake/chip.c | |
| parent | 159520ed7881d1be2fdd02ee13040e8e21a9833c (diff) | |
soc/intel/*: Use SSDT to pass A4GB and A4GS
GNVS is more fragile as you need to keep struct elements in sync with
ASL code.
Change-Id: I2cd5e6b56e4a0dbbb11f4a0ac97e8f84d53b90ec
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/soc/intel/alderlake/chip.c')
| -rw-r--r-- | src/soc/intel/alderlake/chip.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index 59f006634a..6bb55ac78e 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -11,6 +11,7 @@ #include <intelblocks/irq.h> #include <intelblocks/itss.h> #include <intelblocks/pcie_rp.h> +#include <intelblocks/systemagent.h> #include <intelblocks/xdci.h> #include <soc/intel/common/vbt.h> #include <soc/itss.h> @@ -188,6 +189,7 @@ static struct device_operations pci_domain_ops = { .scan_bus = &pci_domain_scan_bus, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = &soc_acpi_name, + .acpi_fill_ssdt = ssdt_set_above_4g_pci, #endif }; |