summaryrefslogtreecommitdiff
path: root/src/soc/amd
AgeCommit message (Collapse)Author
2023-08-08soc/amd/common/include/data_fabric_defs: introduce & use DF_REG_* macrosFelix Held
To have both the PCI function number and the register offset into the config space of that function of the data fabric device in the data fabric register definitions, introduce and use the DF_REG_ID, DF_REG_FN and DF_REG_REG macros. The DF_REG_ID macro is used for register definitions where both the function number and the register offset are specified, and the DF_REG_FN and DF_REG_REG macros are used to extract the function number and the register offset from the register defines. This will allow having one define for accessing an indexed group of registers that are on different functions of the data fabric device. TEST=MMIO resources read from the data fabric's MMIO decode registers don't change on Mandolin and the ACPI CRAT table is also identical. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I63a284b26081c170a217b082b100c482f6158e7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/76886 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-08ACPI: Add helper fill_fadt_extended_pm_io()Kyösti Mälkki
Once platform code has filled in the (legacy) ACPI PM register map, added function will fill in the extended entries in FADT. TEST=samsung/lumpy and amd/mandolin FADT stays unchanged. Change-Id: I90925fce35458cf5480bfefc7cdddebd41b42058 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-06device, soc: Add SPDX license headers to MakefilesMartin Roth
To help identify the licenses of the various files contained in the coreboot source, we've added SPDX headers to the top of all of the .c and .h files. This extends that practice to Makefiles. Any file in the coreboot project without a specific license is bound to the license of the overall coreboot project, GPL Version 2. This patch adds the GPL V2 license identifier to the top of all makefiles in the device and soc directories that don't already have an SPDX license line at the top. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I89c05c7c1c39424de2e3547c10661c7e3f58b8f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2023-08-05src/*/post_code.h: Change post code prefix to POSTCODEYuchen He
The prefix POSTCODE makes it clear that the macro is a post code. Hence, replace related macros starting with POST to POSTCODE and also replace every instance the macros are invoked with the new name. The files was changed by running the following bash script from the top level directory. header="src/soc/amd/common/block/include/amdblocks/post_codes.h \ src/include/cpu/intel/post_codes.h \ src/soc/intel/common/block/include/intelblocks/post_codes.h" array=`grep -r "#define POST_" $header | \ tr '\t' ' ' | cut -d ":" -f 2 | cut -d " " -f 2` for str in $array; do splitstr=`echo $str | cut -d '_' -f2-` grep -r $str src | cut -d ':' -f 1 | \ xargs sed -i'' -e "s/$str/POSTCODE_$splitstr/g" done Change-Id: Id2ca654126fc5b96e6b40d222bb636bbf39ab7ad Signed-off-by: Yuchen He <yuchenhe126@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76044 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-04soc/amd/phoenix: Makefile change to include split hash tableKarthikeyan Ramasubramanian
Include multiple hash tables into relevant CBFS. BUG=b:277292697 TEST=Ensure that all multiple hash tables are part of Myst BIOS image with PSP verstage enabled. Change-Id: I1601f4a01db5b2bbf8b5636ef9e69e41c1d9a980 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76589 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-04soc/amd/phoenix: Add SVC call to inject v2 hash tablesKarthikeyan Ramasubramanian
On mainboards using Phoenix SoC with PSP verstage enabled, to accommodate growing number of PSP binaries, multiple smaller hash tables are introduced. Also some hash tables are in V2 format identifying the concerned PSP binaries using UUID. Add SVC calls to support multiple hash tables with different versions. BUG=b:277292697 TEST=Build and boot to OS in Myst with PSP verstage enabled. Ensure that all the hash tables are injected successfully. Ensure that PSP validated all the signed PSP binaries using the injected hash tables successfully. Change-Id: I64e1b1af55cb95067403e89da4fb31bec704cd4f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76588 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-04soc/amd/common/psp_verstage: Support multiple hash tablesKarthikeyan Ramasubramanian
Currently PSP verstage updates PSP bootloader with one unified hash table containing hashes for all the signed PSP binaries to be validated. With growing number of PSP binaries to validate and memory constraints in PSP, there is a requirement to split and update the hash table into multiple smaller chunks. Hence change the update_psp_fw_hash_table() signature such that the hash tables are updated in a chipset specific way. BUG=b:277292697 TEST=Build and boot to OS in Myst with PSP verstage enabled. Build the Skyrim BIOS image and confirm that the hash table is identical before and after this change. Change-Id: I75aac5bc5e7f61069be25d801d0838fdf565d3d1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76587 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-04soc/amd/common/data_fabric_helper: add comment about cfg_inst_acc_enFelix Held
Since all indirect data fabric register accesses will be non-broadcast accesses that target a specific data fabric instance, the cfg_inst_acc_en bit in the DF_FICAA_BIOS register will always be set since that makes the indirect access target only a specific data fabric instance. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9aff01750c2c1e3506141b3ed293a980a64f8fac Reviewed-on: https://review.coreboot.org/c/coreboot/+/76885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-08-01soc/amd/mendocino: select SOC_AMD_COMMON_BLOCK_CPU_SYNC_PSP_ADDR_MSRMatt DeVillier
Select this Kconfig to ensure the PSP_ADD_MSR is properly programmed across all cores. This resolves a Windows BSOD "CRYPTO_LIBRARY_INTERNAL_ERROR." BUG=b:293571109 BRANCH=skyrim TEST=build/boot google/skyrim, use rdmsr to verify MSR value identical across all cores. Change-Id: I67391b49496d767912f5d81c1758a52a70fca6f6 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76809 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-01soc/amd/common: Redefine EFS_OFFSETZheng Bao
The EFS_OFFSET is the relative address to flash base. We can not assume the flash size is 16M. The change will affect only Gardenia and Pademelon whose flash size are 8M. Change-Id: Ia68032db05264c55d333deec588ad9690a4ed2c1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76764 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-31soc/amd/common/cpu: Add Kconfig to program the PSP_ADDR MSRMatt DeVillier
The PSP_ADDR_MSR is programmed into the BSP by FSP, but not always propagated to the other cores/APs. Add a hook to run a function which will read the MSR value from the BSP, and program it into the APs, guarded by a Kconfig. SoCs which wish to utilize this feature can select the Kconfig. BUG=b:293571109 BRANCH=skyrim TEST=tested with rest of patch train Change-Id: I14af1a092965254979df404d8d7d9a28a15b44b8 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-07-30soc/amd/common/data_fabric/domain: skip reserved resources for ACPIFelix Held
The non-PCI resources added to the domain device are resource consumers, so they mustn't be reported as resource producers. To make sure that this is the case, skip all resources that have the IORESOURCE_RESERVE flag set in amd_pci_domain_fill_ssdt. Commit 7a5dd781d147 ("soc/amd/common/data_fabric/domain: provide amd_pci_domain_fill_ssdt") that introduced amd_pci_domain_fill_ssdt already contained the bug, but since no MMIO range consumers were added back then, the bug only became visible when commit 32169720bb67 ("soc/amd/common/data_fabric/domain: report non-PCI MMIO resources") added the reserved non-PCI MMIO resources to the domain device's resources resulting in MMIO producer objects being generated for MMIO consumers. Those producers that should have been consumers then overlapped with the actual MMIO resource producers which caused Windows to BSOD with an ACPI_BIOS_ERROR. TEST=The non-PCI MMIO resources are no longer added as resource producers and Windows boots again on google/frostflow. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: Matt DeVillier <matt.devillier@gmail.com> Change-Id: Ib099675bc5bea93bf7c2a80f741bef067fd37a58 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76818 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-07-30soc/amd/common/data_fabric/domain: continue after unassigned resourceFelix Held
When iterating over the resource list in amd_pci_domain_fill_ssdt, don't return when a resource is unassigned, but just continue to the next loop iteration so the resulting SSDT will be complete and not broken due to a missing resource template footer and the scope not being closed. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I39fe516f27a6d971fb9c57a1e64ead79d23aff08 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-07-28soc/amd/commonn/block/include/psp_efs.h: Remove unused functionFred Reitberger
Commit 49d8aa7043ea ("soc/amd/common/block/psp: Unmap EFS region after use") removed the 'efs_is_valid' function but left the function signature in the header file. TEST=stoney/picasso/cezanne/mendocino/phoenix builds Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ib596946679b50be63868af57e3428b4d65845419 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76750 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-27soc/amd/noncar/memlayout_x86.ld: Conditionally add fspm regionFelix Held
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1e75f29a52179b72b25092f0ffdfd91a182d6648 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-07-27soc/amd/noncar/memlayout_x86.ld: Move ramstage link addressArthur Heymans
This address is more certain to not collide with other symbols. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I02eddf43a00c443a1193d6db77d6fad3715216f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-07-27soc/amd/noncar/memmap.c: Support non-FSP use casesFelix Held
Without FSP we assume TSEG is right above CBMEM. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8700803617c3fe4890e497c6d7b94f1d36e21cb4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76472 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-27soc/amd/noncar/memmap.c: factor out FSP-specific SMM region codeFelix Held
Factor out the common FSP-specific code to get the location and size of the SMM region from the HOB that FSP has put into memory. This moves FSP-specific code out of the common AMD SoC code into the FSP-specific common AMD SoC code folder. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie137bb0f4e7438a1694810ae71592a34f9d8c86e Reviewed-on: https://review.coreboot.org/c/coreboot/+/76760 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-07-27soc/amd/common/fsp: factor out read_fsp_resources from root_complex.cFelix Held
Factor out the common FSP-specific code to report the usable and reserved memory resources read from the HOBs that FSP has put into memory. This both reduces code duplication and also moves FSP-specific code out of the SoC code into the FSP-specific common AMD SoC code folder. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib373c52030209235559c9cd383f48ee1b3f8f79b Reviewed-on: https://review.coreboot.org/c/coreboot/+/76759 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-07-27soc/amd/cpu.c: Conditionally define .acpi_fill_ssdtFelix Held
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I0e81c08191f3c5f768bd3cad0e4915d4476c739f Reviewed-on: https://review.coreboot.org/c/coreboot/+/76493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-07-25soc/amd/*/root_complex: introduce and use SMN_IOHC_MISC_BASE_13B1Felix Held
On the mobile SoCs, SMN_IOHC_MISC_BASE_13B1 is the only IOHC misc base address, but on for example Genoa it's the address of the IOHC misc base of the second IOHC. Due to it not being the first one on Genoa, use 13B1 as part of the name instead of using an index of 0 which would look odd in the Genoa case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1db28ec03a3ba1c2040d8a1500ae17aa9705f6e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76756 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-07-25soc/amd/*/root_complex: don't report root complex IOAPIC resource twiceFelix Held
Since the per PCI root IOAPIC is now reported as domain MMIO resource and the IVRS code now again probes for the IOAPIC resource on the domain device, the IOAPIC resource doesn't need to be reported as resource of the northbridge PCI device any more. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8604bd321ec4239076b1be99dca095e47f8b75a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76600 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-07-25soc/amd/common/acpi/ivrs: probe IOAPIC device on domain deviceFelix Held
This reverts commit e33d253793f6 ("soc/amd/common/block/acpi/ivrs: fix missing IOAPIC[1] error"). Now that the per PCI root domain IOAPIC MMIO resource is reported on the domain device, we can again probe the resource on the domain device instead of the northbridge PCI device in that domain. This will make the IVRS code compatible again with the work in progress Genoa SoC support. TEST=Linux doesn't complain about the IOAPIC[1] missing in the IVRS on Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib861b19d798fc8ee6603e8803d8d1939be08d275 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76659 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-07-25soc/amd/common/data_fabric/domain: report non-PCI MMIO resourcesFelix Held
Call read_non_pci_resources from amd_pci_domain_read_resources to tell the resource allocator about the non-PCI MMIO regions within the data fabric MMIO regions so that the allocator won't place any PCI MMIO in the same areas. TEST=On Mandolin 3 new non-PCI resources get reported to the allocator: avoid_fixed_resources: DOMAIN: 0000 04 base fd100000 limit fd1fffff mem (fixed) avoid_fixed_resources: DOMAIN: 0000 05 base fd000000 limit fd0fffff mem (fixed) avoid_fixed_resources: DOMAIN: 0000 20000120 base fec01000 limit fec01fff mem (fixed) Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7f69b86e376e3368d4f156ccf93791cc00886489 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-25soc/amd/glinda/root_complex: add non-PCI MMIO registersFelix Held
Add the SoC-specific non-PCI MMIO register list. PPR #57254 Rev 1.52 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I29b4ef947776ab8a6c215c1a5204769a9f61e6fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/76598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-07-25soc/amd/phoenix/root_complex: add non-PCI MMIO registersFelix Held
Add the SoC-specific non-PCI MMIO register list. PPR #57019 Rev 3.05 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6f57df6ca09f1583409f6c4e68177b05b9f31def Reviewed-on: https://review.coreboot.org/c/coreboot/+/76597 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-25soc/amd/mendocino/root_complex: add non-PCI MMIO registersFelix Held
Add the SoC-specific non-PCI MMIO register list. PPR #57243 Rev 3.02 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2c5173e596f3f3f1c63165871178dbbd0e9641be Reviewed-on: https://review.coreboot.org/c/coreboot/+/76596 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-07-25soc/amd/cezanne/root_complex: add non-PCI MMIO registersFelix Held
Add the SoC-specific non-PCI MMIO register list. PPR #56569 Rev 3.04 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id99c64c172481984306814980a1ddf0b2d535413 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-07-25soc/amd/picasso/root_complex: add non-PCI MMIO registersFelix Held
Add the SoC-specific non-PCI MMIO register list. PPR #55570 Rev 3.18 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If7bfcdd9b70b71fe6aedcab3694698967d48e18e Reviewed-on: https://review.coreboot.org/c/coreboot/+/76554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-07-25soc/amd/common/root_complex: add function to report non-PCI resourcesFelix Held
Introduce the common read_non_pci_resources function to read the base address of the non-PCI resources within the MMIO regions configured in the data fabric registers and pass that info to the resource allocator. Each SoC will need to provide implementations for get_iohc_misc_smn_base and get_iohc_non_pci_mmio_regs in order for read_non_pci_resources to know the SoC-specific base addresses, register offsets and MMIO region sizes. In case of SoCs with only one PCI root domain, the domain parameter of get_iohc_misc_smn_base will be unused, but in the case of SoCs with more than one PCI root domains, this parameter will be used by the SoC-specific code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If9aca67fa0f5a0d504371367aaae5908bcb17dd9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-07-24soc/amd/*/Makefile.inc: Do not add APOB NV entry when disabledFred Reitberger
Do not add type 0x63 entry to amdfw.rom when APOB_NV cache is disabled. BUG=b:290763369 TEST=boot birman multiple times with/without APOB_NV cache enabled Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Iefe6f56d7dbedd289680f25a5f372eaa12e967b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76568 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-24mb/google/myst: Disable APOB NVFred Reitberger
Disable the APOB cache for only Myst, and re-enable APOB for other Phoenix SOC mainboards. BUG=b:290763369 TEST=verify APOB cache is disabled Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ie611e0b84611b2f50c989c75612fc2186b2dbfdf Reviewed-on: https://review.coreboot.org/c/coreboot/+/76567 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-07-24soc/amd/common/block/apob: Add Kconfig option to disable APOB NVFred Reitberger
Add Kconfig option to disable the non-volatile APOB cache for a mainboard using an SOC that supports APOB. BUG=b:290763369 TEST=verify APOB cache is disabled when selected Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I0170355bbf29ea6386fa69a318e61f057b9a9a3f Reviewed-on: https://review.coreboot.org/c/coreboot/+/76566 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-07-24soc/amd/phoenix/Makefile.inc: Enable amdfw manifestFred Reitberger
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ic030f91bbfd7226d7adbbe83a2f9e7930af46207 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-07-21vendorcode/amd/fsp/common: Refactor dmi_info.hKonrad Adamczyk
SoC family is able to provide SoC-specific information via amd/fsp/<soc_family>/soc_dmi_info.h. Use common amd/fsp/common/dmi_info.h for all AMD platforms. This way, duplicated dmi_info.h files in vendorcode/amd/fsp/<soc_family>/ can be removed. BUG=b:288520486 TEST=Dump `dmidecode -t 17`. Change-Id: I5e0109af51b78360f7038b20a2975aceb721a7d5 Signed-off-by: Konrad Adamczyk <konrada@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76107 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-20soc/amd/common/pi: Ensure AGESA S3 resume called before SMM lockMatt DeVillier
AGESA S3 restore needs to occur before SMM finalization/locking, but it's a crapshoot as to which runs first since both use the same BS_OS_RESUME/BS_ON_ENTRY boot state callback, and there's no way to prioritize/force ordering. To work around this, move the AGESA S3 resume call to the preceding boot state (BS_OS_RESUME_CHECK) to ensure it runs first, and guard it to ensure it only runs on the S3 resume path. BUG=none TEST=build/boot google/liara, verify S3 resume successful. Change-Id: I765db140c6708a0b129f79fb7d3dc8a4ab3095bd Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76592 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2023-07-20soc/amd/common/smn/Kconfig: expand SMN acronymFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icce4092f1e09d492e0faf4b5e85525871614d73d Reviewed-on: https://review.coreboot.org/c/coreboot/+/76607 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-07-20soc/amd/common/block/smn: add smn_read64Felix Held
Add smn_read64 which calls smn_read32 twice to read two adjacent 32 bit SMN registers and merges the results into a 64 bit value which it then returns. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib2d58ec9818559cbefd7b819ae311ad02fafa18f Reviewed-on: https://review.coreboot.org/c/coreboot/+/76552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-07-18include/cpu/amd/msr: introduce and use PSTATE_MSR_COUNTFelix Held
Add and use a define for the total number of P-state MSRs to avoid magic constants in the code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I37a89faa0f216790b3404fc03edc62408684cc24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-07-18soc/amd/stoneyridge/pstate_util: fix off by one in P-state MSR numberFelix Held
There are 8 P-state MSRs and not only 7. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic2899b6e454233c6cbb8fc1e439ff069c4d3d3a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-07-18soc/amd/*/root_complex.c: Use newer function for resource declarationsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: If2048c9cade731b2e4464d0670e0578f5f4bcea0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-07-18soc/amd/stoneyridge: Use newer function for resource declarationsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I2d01424731b149daa3d3378d66855ee5e074473b Reviewed-on: https://review.coreboot.org/c/coreboot/+/76290 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-07-17soc/amd/common/acpimmio: factor out IO port access to PM registersFelix Held
Factor out all functions that use the indirect IO port based access to the PM registers into a new compilation unit and only select it on platforms that support this interface. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If9c059e450e2137f7e05441ab89c1f0e7077be9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/76458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-07-17soc/amd/common/pm/pmlib: use PM register mapping in ACPIMMIO regionFelix Held
In all SoC pm_set_power_failure_state gets called either after a call to enable_acpimmio_decode_pm04() or the ACPIMMIO mapping is already enabled after reset on the SoC. This allows to use pm_read8 and pm_write8 that use the ACPIMMIO mapping of the PM registers instead of pm_io_read8 and pm_io_write8 which won't work on Phoenix and Glinda due to the IO ports used on older generations to access to the PM registers not being implemented any more. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id0d0523d2c4920da41b3fb73cf62f22a60f1643a Reviewed-on: https://review.coreboot.org/c/coreboot/+/76463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-07-17soc/amd/common/lpc/lpc_util: use PM register mapping in ACPIMMIO regionFelix Held
In all SoC lpc_early_init gets called either after a call to enable_acpimmio_decode_pm04() or the ACPIMMIO mapping is already enabled after reset on the SoC. This allows to use pm_read8 and pm_write8 that use the ACPIMMIO mapping of the PM registers to set the PM_LPC_ENABLE bit in the PM_LPC_GATING register instead of pm_io_read8 and pm_io_write8 which won't work on Phoenix and Glinda due to the IO ports used on older generations to access to the PM registers not being implemented any more. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8b31ec4e03a06796502c89e3c2cfaac2d41b0ed9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76461 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-17soc/amd/common/acpimmio/mmio_util: drop enable_acpimmio_decode_pm24Felix Held
None of the platforms that used enable_acpimmio_decode_pm24 is in the tree any more, so drop this function. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iea345a825c4581bf2acb932692ebcad2a7a5b4ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/76457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-07-17soc/amd/glinda/early_fch: don't call enable_acpimmio_decode_pm04Felix Held
The enable_acpimmio_decode_pm04 function uses the IO port based indirect access of the PM register space. The PM_INDEX and PM_DATA registers don't exist any more on Glinda, so the code shouldn't access those. Since the PM_04_ACPIMMIO_DECODE_EN bit in the ACPIMMIO_DECODE_REGISTER_04 register is 1 after reset, the ACPIMMIO space is still accessible. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic6bc0479ea4ea2b9fe3629a6e15940b31b2864d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-07-17soc/amd/phoenix/early_fch: don't call enable_acpimmio_decode_pm04Felix Held
The enable_acpimmio_decode_pm04 function uses the IO port based indirect access of the PM register space. The PM_INDEX and PM_DATA registers don't exist any more on Phoenix, so the code shouldn't access those. Since the PM_04_ACPIMMIO_DECODE_EN bit in the ACPIMMIO_DECODE_REGISTER_04 register is 1 after reset, the ACPIMMIO space is still accessible. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia41f239b023edc094f5cbae63ed7c079649c74da Reviewed-on: https://review.coreboot.org/c/coreboot/+/76437 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-14soc/amd/common: Add warning if microcode CBFS filename is in useMartin Roth
Because of the way that the CBFS filename is generated from the contents of the microcode patch, if a duplicate microcode patch is included in the build, the makefile would create a second copy of the name, which doesn't work. This led to "odd" results where the other attributes of the first copy were erased, causing cbfstool to fail. The cause of the failure is not immediately obvious, and is a little difficult to track down. This patch causes an immediate failure and gives a reason as to the cause of the issue. When a failure is seen, this is the result: File1: 3rdparty/amd_blobs/phoenix/psp/TypeId0x66_UcodePatch_PHXn4_A0.bin File2: 3rdparty/amd_blobs/phoenix/psp/TypeId0x66_UcodePatch_PHX4_A0.bin src/soc/amd/common/block/cpu/Makefile.inc:25: *** Error: The cbfs filename "cpu_microcode_a740.bin" is used for both above files. Check your microcode patches for duplicates.. Stop. TEST=Now checked for both positive and negative failures. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I3d34dc5585182545bdcbfa6370ebc34aa767cae2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76423 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-14soc/amd/phoenix: Disable APOB CacheKarthikeyan Ramasubramanian
There is a data abort in ABL when the memory training data is used from APOB Cache. Disable APOB Cache until the cause is identified. The downside of this change is that the memory training happens in every boot cycle. BUG=b:290763369 TEST=Build BIOS image and boot to OS in Myst. Trigger a reboot from AP console and ensure that the system boots to OS. Change-Id: I20f4f40cdaac68bca6e121e3a238d13fe80d0d3c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-07-14mb/google: AMD: move tpm_tis to AMD common codeGrzegorz Bernacki
It moves cr50_plat_irq_status() to common code and adds Kconfig option to specify GPIO used for interrupt. BUG=b:277787305 TEST=Build all affected platform and confirm using right GPIO number. Tested on Skyrim. Change-Id: I775c4e24cffee99b6ac3e05b58a75425029a86c8 Signed-off-by: Grzegorz Bernacki <bernacki@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75621 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-07-12soc/amd/common: Use newer function for resource declarationsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Iad8b7c705d5053700850065f90314444904b5b54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76289 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-07-07soc/amd/*/globalnvs,nvs: remove deprecated & unused CBMC field from GNVSFelix Held
Commit cde4f3b2790d ("acpi/gnvs.c: Drop unused pointer to the cbmem console") removed writing the coreboot memory console pointer to the GNVS and kept the CBMC field as reserved. Since those fields aren't needed any more and there are no dependencies on the absolute position of the different fields in GNVS as long as both GNVS definitions on the C and the ASL side match, remove the deprecated and unused CBMC field from the GNVS structs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iadfaf5a4ec1401b027dbfb6a7c6ce74a1dcecdfa Reviewed-on: https://review.coreboot.org/c/coreboot/+/76351 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-07-07soc/amd/*/Makefile.inc: Use _tohex instead of printfFred Reitberger
Use the _tohex function to convert values to hex instead of 'shell printf' TEST=timeless builds identical for grunt,dalboz,guybrush,chausie,birman Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ic7f7d1b764479088cc0980b208d8d603bc712832 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76314 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-07-06acpi/gnvs.c: Drop unused pointer to the cbmem consoleArthur Heymans
Change-Id: I7e2018dbccead15fcd84e34df8207120d3a0c57c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64303 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-07-05soc/amd/phoenix/Makefile.inc: Refactor repeated lines to a variableFred Reitberger
Rather than repeat the same line multiple times, save it in a variable once and use that variable in the rest of the file. TEST=timeless birman build identical Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I4eb262adb3bbda04add79b2e2b8bee9a609a1e5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/76197 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-05soc/amd/phoenix/Makefile.inc: Pass APOB_NV address as offsetFred Reitberger
Pass the APOB NV address as a flash offset instead of x86 address. TEST=boot birman and verify APOB_NV is working Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I0f710f12cc5d933a75840dbce1c4bad0c2ea04cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/76162 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-04soc/amd/common/block/acpi/ivrs: use IOMMU PCI register definitionsFelix Held
Use IOMMU_CAP_BASE_[LO,HI] instead of magic values. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7032d9f032a22649951ef1535f39b918eb8bd539 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-04soc/amd/common/block/iommu: factor out PCI register definitionsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie155cab1f659e9f7b64cd87ba8a77260056656d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76222 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-04soc/amd/common/block/uart: remove DRIVERS_UART_8250MEMEric Lai
Select DRIVERS_UART_8250MEM_32 will select DRIVERS_UART_8250MEM too. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I87a47e2d76ab7a0717edf725bf94d87f9f2357f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76184 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-07-03soc/amd/phoenix/Kconfig: Select VBOOT_X86_SHA256_ACCELERATIONFred Reitberger
Phoenix is an x86 soc that supports sha256 instructions. TEST=boot birman to chromeos Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Id228399ba02708b97110d524ce12c2626588762d Reviewed-on: https://review.coreboot.org/c/coreboot/+/76166 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-07-03soc/amd/phoenix: Remove TODO after reviewFred Reitberger
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ifd2b53ff24776238190eb946db7b12827fcfc804 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-07-03soc/amd/*: Utilize get_fmap_value() Makefile function where possibleMatt DeVillier
Replace: $(shell awk '$$2 == "xyz" {print $$3}' $(obj)/fmap_config.h) with: $(call get_fmap_value,xyz) to improve code readability/maintainability. Change-Id: If6859108c7d5611a63fc38909dc75195bfb1d59a Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76168 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-06-29soc/amd/phoenix/Kconfig: Drop TODO for FSP_DMI_TABLESKonrad Adamczyk
BUG=b:288520486 TEST=In kernel, dump `dmidecode -t 17`. Change-Id: I1a8aae12ec449fe921814a6e363306fced969367 Signed-off-by: Konrad Adamczyk <konrada@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76109 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-06-29soc/amd/common/fsp: Fix dimm_num assignmentKonrad Adamczyk
The dimm_num shall be dimm, not channel. BUG=b:288520486 TEST=In kernel, see output from `dmidecode -t 17`. Observe that Locator reflects proper location of the module. Change-Id: Id876a5c245ed1a145c930b3456830d7b42780b74 Signed-off-by: Konrad Adamczyk <konrada@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-06-28soc/amd/common/block/acpi/ivrs: fix missing IOAPIC[1] errorFelix Held
When probing the resource with the IOMMU_IOAPIC_IDX index, we need to use the PCI device 0 function 0 on the first bus in the domain for probing and not the domain device, since the resource isn't on the domain device, but on the northbridge device which is B0F0D0 in the case of the APUs. TEST=This fixes the following error on Mandolin with Picasso: AMD-Vi: [Firmware Bug]: : IOAPIC[1] not in IVRS table AMD-Vi: Disabling interrupt remapping Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id88f17d68ba5accef6561837478828bd3d24baa5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76117 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-06-27soc/amd/block/ivrs: Add NULL check for IVRSNaresh Solanki
Add NULL check for ivrs pointer before use. Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Change-Id: Ibeb0ea3bcaa3512a93500588ad4f11046edee61f Reviewed-on: https://review.coreboot.org/c/coreboot/+/75506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-06-26soc/amd/common/iommu.c: Make sure iommu is enabledArthur Heymans
Don't rely on vendorcode to set enable bit on IOMMU. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Change-Id: I1805a20656b7fb3915f8cc93c618ee074461840f Reviewed-on: https://review.coreboot.org/c/coreboot/+/75829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-06-26soc/amd/common/block/acpi/ivrs: zero-initialize ivhd_[range,entry]Felix Held
Zero-initialize the ivhd_range and ivhd_entry structs to make sure that the whole struct is in a defined state. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iccacc89bfc497449ad0716a3436949505b65f748 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76079 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-26soc/amd/common/block/acpi/ivrs: use size of instance instead of typeFelix Held
To determine the length parameter of memset, use sizeof with the instance as argument instead of the type. The behavior is the same, but it clarifies parameters in the memset call a bit. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I63674fbed7097a583cd77fa6e700652d6dcc5565 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-06-26soc/amd/common/block/acpi/ivrs: use memset on ivhd_[11,40]Felix Held
Assign the current address casted to acpi_ivrs_ivhd[11,40]_t pointer to *ivhd_[11,40] at the beginning of acpi_fill_ivrs[11,40] and then use memset on *ivhd_[11,40] to zero-initialize the structs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I70b12fee99d6c71318189ac35e615589a4c8c629 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76077 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-23soc/amd/common/block/acpi/ivrs: zero-initialize ivhd_hpet structFelix Held
Zero-initialize the ivhd_hpet struct right at the beginning of the ivhd_describe_hpet function to make sure that the whole struct is in a defined state. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If4d3563c485eed4a7cb0526a62f7b6c80f763bfd Reviewed-on: https://review.coreboot.org/c/coreboot/+/76074 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-06-23soc/amd/common/acpi/ivrs: add HID argument to ivhd_describe_f0_deviceFelix Held
Allow the caller to specify the HID that gets written to the ivrs_ivhd_f0_entry_t struct. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I830f1fbbd535b100c88997ece10142a5d553950f Reviewed-on: https://review.coreboot.org/c/coreboot/+/76073 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2023-06-23soc/amd/common/block/acpi/ivrs: zero-initialize ivhd_f0 structFelix Held
Zero-initialize the ivhd_f0 struct right at the beginning of the ivhd_describe_f0_device function to make sure that the whole struct is in a defined state. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia6750b58dacb9b9192ed21128eb6e3a4495b96d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2023-06-23soc/amd/common/block/acpi/ivrs: conditionally generate eMMC entryFelix Held
The eMMC entry in the IVRS table should only be generated if an eMMC controller is present in the SoC. Where the PCI_DEVFN(0x13, 1) is from is currently unclear to me. There is no PCI device 0x13 on bus 0 and the eMMC controller is also an MMIO device and not a PCI device, but this is what the reference code does. My guess would be that it mainly needs to be a unique PCI device that won't collide with any existing PCI device in the SoC. Add a comment about this too. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I00865cb7caf82547e89eb5e77817e3d8ca5d35dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/75933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-06-23Makefile.inc: don't add fmap_config.h dependency twiceFelix Held
Commit d054bbd4f1ba ("Makefile.inc: fix multiple jobs build issue") added a dependency on $(obj)/fmap_config.h to all .c source files in all stages, so it's not needed any more to add it as a dependency to files that include fmap_config.h. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7b62917f32ae9f51f079b243a606e5db07ca9099 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76002 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-06-23commonlib/console/post_code.h: Change post code prefix to POSTCODElilacious
The prefix POSTCODE makes it clear that the macro is a post code. Hence, replace related macros starting with POST to POSTCODE and also replace every instance the macros are invoked with the new name. The files was changed by running the following bash script from the top level directory. sed -i'' '30,${s/#define POST/#define POSTCODE/g;}' \ src/commonlib/include/commonlib/console/post_codes.h; myArray=`grep -e "^#define POSTCODE_" \ src/commonlib/include/commonlib/console/post_codes.h | \ grep -v "POST_CODES_H" | tr '\t' ' ' | cut -d ' ' -f 2`; for str in ${myArray[@]}; do splitstr=`echo $str | cut -d '_' -f2-` grep -r POST_$splitstr src | \ cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g"; grep -r "POST_$splitstr" util/cbfstool | \ cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g"; done Change-Id: I25db79fa15f032c08678f66d86c10c928b7de9b8 Signed-off-by: lilacious <yuchenhe126@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-22soc/amd/common/psp_verstage: move post codes to own headerlilacious
In order to clean up the post code macros, move them to a separate header away from unrelated code. The new header file is included in the file where the post codes are moved out of, so that the current state remains unchanged. Change-Id: I28a932ce071488e90000e1bbd30b4d739a4bae43 Signed-off-by: lilacious <yuchenhe126@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-20soc/amd/common/iommu: Use preprocessor values for IOMMU baseArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I85f58565bf1f955f704e223d538d0b374bc6fbda Reviewed-on: https://review.coreboot.org/c/coreboot/+/75915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-06-19soc/amd/common/block/include/amdblocks/data_fabric: fix typo in 'IOAPIC'Felix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie17fd14bed9ec91c5f11aee00bf5d2d2e253ec08 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75897 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19soc/amd/*: Use proper resource function to declare GNB IOAPICsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I296697d579b9ad8e35b22ada939a74a5ef6d6f61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75828 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-15soc/amd/*/root_complex: reserve IOMMU MMIO areaFelix Held
This makes sure that the resource allocator won't use this address range for anything else. In the systems I looked at, this was between the end of the above 4GB memory and the beginning of the above 4GB PCI BAR MMIO region, but better reserve it here so nothing else will get allocated there if this expectation isn't met. TEST=Reserved region is printed in the console logs: update_constraints: PCI: 00:00.0 09 base fd00000000 limit fdffffffff mem (fixed) Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5a8150873cb019ca1d903ed269e18d6f9fabb871 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-06-14soc|vc/amd/phoenix: Prepare for PSP verstageKarthikeyan Ramasubramanian
Update all the required sources to lay the ground work to enable PSP verstage. BUG=b:284984667 TEST=Build Myst BIOS image with PSP verstage enabled. Change-Id: I6fbb1f835ac2ad6ff47f843321e1bd380af7ce33 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75584 Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-06-14acpi/acpi.h: Remove global acpi_fill_ivrs_ioapic()Arthur Heymans
In soc/amd this function is unused so drop it and rename _acpi_fill_ivrs_ioapic(). Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ic403fd84cb9cd5805fbc6f0c5a64cefbf4b0cd81 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
2023-06-14soc/amd/acpi/ivrs: Use specific IOMMU resource index on all SOCArthur Heymans
By adding all DXIO IOAPIC with the same resource index, the IVRS code can always pick that resource which simplifies the code. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I10345e2337dcb709c2c1a8e57a1b7dd9c04adb9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/75710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
2023-06-13soc/amd/common/cpu/noncar/cpu: rename get_smee_reserved_address_bitsFelix Held
Rename get_smee_reserved_address_bits to get_sme_reserved_address_bits since the feature is called secure memory encryption and the last 'e' in SMEE bit in the SYSCFG MSR just stands for enable. The function will return a valid number of reserved address bits no matter if this is enabled or not, so drop the second 'e'. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3795f7a861e39cb6c8209fee10191f233cbcd308 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-06-12soc/amd/stoney: Expand the SMM region for cacheZheng Bao
Currently the data to be put to cache region is 0x14FF90. With the limit size 0x150000, the data for S3 can not be put into. So we expand it a little. Change-Id: If6b03b713059c54c7dae8f2db0f6426d8aa1aab1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69782 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-12soc/amd/smm: Sanity check the SMM TSEG sizeZheng Bao
As per AMD64 Architecture Programmer's Manual, section 10.2.5 SMRAM Protected Areas: The TSEG range must be aligned to a 128 Kbyte boundary and the minimum TSEG size is 128 Kbytes. The SMM TSEG size should be less than SMM reserved size. AMD TSEG mask works like an MTRR. It needs to be aligned to it's size and it's size needs to be a power of 2. Change-Id: Ic4f557c7b77db6fc5ab2783ca4e2ebe7a4476e85 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75405 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-12soc/amd/block/ivrs: Generalize IVRS table generationNaresh Solanki
This commit introduces a refactored version of the IVRS (I/O Virtualization Reporting Structure) table generation. The main objective of this refactoring is to generalize the process of generating the IVRS table based on the IOMMU (Input/Output Memory Management Unit) domains and their corresponding resources. Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Change-Id: Ic471f05d6000c21081d70495b7dbd4350e68b774 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75451 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-09soc/amd/phoenix/Kconfig: temporary drop VGA_BIOS_FILEFelix Held
The file VGA_BIOS_FILE points to is right now the Mendocino VBIOS. Since the default value probably shouldn't point to a location in site-local, drop this for now, but leave a TODO to put that back once the correct VBIOS files are available in 3rdparty/amd_blobs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifbc6cbe1e371d8d247f86555a5361ed237897dea Reviewed-on: https://review.coreboot.org/c/coreboot/+/75484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-06-09soc/amd: add ops xhci_pci_ops to XHCI controllers in devicetreeFelix Held
Instead of adding the new PCI IDs of the XHCI controllers in every new chip generation to the pci_xhci driver, bind the driver to the internal PCI devices of the XHCI controllers via the device ops statement in the chipset devicetree. The PCI device function of the XHCI2 controller in Mendocino can be either a dummy device or the XHCI controller, so the device ops are attached to that device in the mainboard devicetree instead. The Glinda code is right now just a copy of the Mendocino code, so it'll change in the future, but for consistency the equivalent changes to those in Mendocino are applied there too. Since the device ops are now attached to the devices via the static devicetree entry, also remove both the xhci_pci_driver struct and the amd_pci_device_ids array from drivers/usb/pci_xhci/pci_xhci.c. TEST=SSDT entries for the XHCI controllers are still generated on Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9c455002c6d2aac576fe24eee0c31744b4507bb0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-08soc/amd/stoneyridge/acpi/northbridge: drop _STA method from PCI0 scopeFelix Held
The PCI root complex itself isn't on an enumerable bus, so without providing an _STA method, the device will still be assumed to be present and visible, so this won't change behavior. This also brings Stoneyridge more in line with the newer SoCs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I663c7bcba89ffe25d0819d83461cb95e10f49028 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75671 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-08soc/amd/picasso/acpi/northbridge: drop _STA method from PCI0 scopeFelix Held
The PCI root complex itself isn't on an enumerable bus, so without providing an _STA method, the device will still be assumed to be present and visible, so this won't change behavior. This also brings Picasso more in line with Cezanne and newer SoCs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Nico Huber <nico.h@gmx.de> Change-Id: Ied48b48113f6e871e90d17cbd216be003f05b5ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/74993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-06-08soc/amd/phoenix: Hook up xhci ops in chipset.cbEric Lai
Hook up xhci ops for Phoenix xHCI device. Benefit is we don't have to bother by adding xhci DID. BUG=b:285981912 TEST=check coreboot log shows below. [INFO ] \_SB.PCI0.GP41.XHC0.RHUB.SS01: USB3 Type-A Port A0 (MLB) Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ib59874948725966b04b54def3f6de463afeda709 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-06-07soc/amd/*/root_complex: use VGA_MMIO_* definesFelix Held
Replace the magic constants by using defines. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I16179a37b6ee19bc3b4862b7dcb3bbc4caf63f2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/75668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-06-07soc/amd/stoneyridge/acpi/sb_pci0_fch: use VGA_MMIO_* definesFelix Held
Replace the magic constants by using defines. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I94ad285a2c5712d352d4f92697fc3140847d88de Reviewed-on: https://review.coreboot.org/c/coreboot/+/75667 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-07soc/amd/stoneyridge/northbridge: use VGA_MMIO_* definesFelix Held
Replace the magic constants by using defines. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6303e5a697a7ad09a48cb7a2c79fa76f4c6ce232 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-06-07soc/amd/glinda/acpi: use ROOT_BRIDGE macroFelix Held
Use the ROOT_BRIDGE macro in soc.asl to replace the pci0.asl file. The soc/amd/common/acpi/lpc.asl file which was included in the now removed pci0.asl file now gets included in the correct scope in the soc.asl file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I373c171f7f4754391012b41d44965561ced4f0b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75595 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-07soc/amd/phoenix/acpi: use ROOT_BRIDGE macroFelix Held
Use the ROOT_BRIDGE macro in soc.asl to replace the pci0.asl file. The soc/amd/common/acpi/lpc.asl file which was included in the now removed pci0.asl file now gets included in the correct scope in the soc.asl file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If293188fc8d0ff41b47ab84c9655333e9ebe58e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-06-07soc/amd/mendocino/acpi: use ROOT_BRIDGE macroFelix Held
Use the ROOT_BRIDGE macro in soc.asl to replace the pci0.asl file. The soc/amd/common/acpi/lpc.asl file which was included in the now removed pci0.asl file now gets included in the correct scope in the soc.asl file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6fc4b09f79e633208ab7536543c876c2c6129eb3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75593 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>