diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-07-18 20:37:04 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-07-25 13:32:58 +0000 |
| commit | 3b3d8025e7b26c3ed995c8b7a014ff73b4ccc80a (patch) | |
| tree | 81788680505575f26f0fe203d7e15a5a1bae6f67 /src/soc/amd | |
| parent | 43662b53cb3a5999b5f1506338d7ef4b79bf41e5 (diff) | |
soc/amd/cezanne/root_complex: add non-PCI MMIO registers
Add the SoC-specific non-PCI MMIO register list. PPR #56569 Rev 3.04 was
used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id99c64c172481984306814980a1ddf0b2d535413
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/cezanne/root_complex.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c index b6a28d40ee..0ddce95a8a 100644 --- a/src/soc/amd/cezanne/root_complex.c +++ b/src/soc/amd/cezanne/root_complex.c @@ -7,6 +7,7 @@ #include <amdblocks/ioapic.h> #include <amdblocks/iomap.h> #include <amdblocks/memmap.h> +#include <amdblocks/root_complex.h> #include <arch/ioapic.h> #include <arch/vga.h> #include <cbmem.h> @@ -206,3 +207,28 @@ struct device_operations cezanne_root_complex_operations = { .acpi_name = gnb_acpi_name, .acpi_fill_ssdt = root_complex_fill_ssdt, }; + +uint32_t get_iohc_misc_smn_base(struct device *domain) +{ + return 0x13b10000; +} + +static const struct non_pci_mmio_reg non_pci_mmio[] = { + { 0x2d8, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, + { 0x2e0, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, + { 0x2e8, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, + /* The hardware has a 256 byte alignment requirement for the IOAPIC MMIO base, but we + tell the FSP to configure a 4k-aligned base address and this is reported as 4 KiB + resource. */ + { 0x2f0, 0xffffffffff00ull, 4 * KiB, IOMMU_IOAPIC_IDX }, + { 0x2f8, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, + { 0x300, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, + { 0x308, 0xfffffffff000ull, 4 * KiB, NON_PCI_RES_IDX_AUTO }, + { 0x318, 0xfffffff80000ull, 512 * KiB, NON_PCI_RES_IDX_AUTO }, +}; + +const struct non_pci_mmio_reg *get_iohc_non_pci_mmio_regs(size_t *count) +{ + *count = ARRAY_SIZE(non_pci_mmio); + return non_pci_mmio; +} |