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2023-01-13soc/amd/phoenix: use common SMU S3/4/5 entry message codeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie7ded68f4732ec12a1c7e59445d572763a03c3b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71879 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-13soc/amd/mendocino: use common SMU S3/4/5 entry message codeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ief1e9c6d6fa0889b947863837bedb2fbdf3120c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71878 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-13soc/amd/cezanne: use common SMU S3/4/5 entry message codeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4b9f1b71a5f8b2776c8b338351b2cca723d00598 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71877 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-13soc/amd/picasso: use common SMU S3/4/5 entry message codeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iedd99cfb64809c4e111e0931c2260981f465035b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-13soc/amd: introduce common SMU S3/4/5 entry message codeFelix Held
The smu_sx_entry function is identical for all AMD SoCs, so introduce it as common code that can be selected to be included in the build via the SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY Kconfig option. The only SoC-specific difference in this function is the ID of the SMC_MSG_S3ENTRY message which is defined in each SoC's soc/smu.h include file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I49758e9333a351d8e50e8f1b53a7f00fbe89866c Reviewed-on: https://review.coreboot.org/c/coreboot/+/71875 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-13soc/amd/glinda: Use common fsp-s preloaderFred Reitberger
Use the common preloader for fsp-s Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I32f8ca02c4de9e882f207c2dd2378b6b44dc61ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/71848 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-13soc/amd/phoenix: Use common fsp-s preloaderFred Reitberger
Use the common preloader for fsp-s Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Iea7011d37667f3f04ce842038346741fba66b1dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/71847 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12soc/amd/mendocino: Use common fsp-s preloaderFred Reitberger
Use the common preloader for fsp-s Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I74ef10347c37c8371156f89da9f234d170ab1aa6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71846 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-12soc/amd/cezanne: Use common fsp-s preloaderFred Reitberger
Use the common preloader for fsp-s Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ibbed17445c3cd8fa4da671f2a90532d3c39ad08b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-12soc/amd/common/fsp: Introduce SOC_AMD_COMMON_FSP_PRELOAD_FSPSFred Reitberger
The function to start preloading the fsp-s is identical in cezanne and newer socs, so move it to common with a new Kconfig option to enable it. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ia572c99928f4a60896b7a861ab6fb3f1257ac1cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/71844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-12soc/amd/mendocino/include/soc/southbridge.h: Use BIT macro for consistencyFred Reitberger
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I2dd17774b79c5adb64c2575ac55dec476c434842 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71843 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-12soc/amd/mendocino: Remove TODO after reviewFred Reitberger
Remove TODO comment after reviewing against mendocino ppr #57243, rev 3.00 BUG=b:263563246 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Id517ce6e5f5bee5deffe509d748b16be0eefca96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2023-01-12soc/amd/mendocino/include/platform_descriptors: remove TODO after reviewFelix Held
This header file is correct for Mendocino, so remove the TODO. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I85b47491863bff731b86cf0523253cb547dbb76a Reviewed-on: https://review.coreboot.org/c/coreboot/+/71794 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12treewide: Remove unused <cpu/amd/mtrr.h>Elyes Haouas
Change-Id: Ibff33c08a1d583b19b205a66d5a4267df65ced75 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-123rdparty/amd_blobs:Advance submodule pointerJason Glenesk
This picks up the following changes: acf73954 phoenix: rename morgana to phoenix a2c15297 mendocino: Upgrade SMU to 90.35.166 28983855 Update Picasso FSP binaries This also updates the phoenix fw.cfg file that points to the submodule. Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I1d04d6232307dc913645a3d60ac3711018e2bdfb Reviewed-on: https://review.coreboot.org/c/coreboot/+/71803 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12soc/amd: Change Morgana codename to PhoenixMartin Roth
Now that the next generation of APUs is officially announced, we can unmask morgana. The chip formerly known as Morgana is actually Phoenix. Surprise! This patch just changes the name across the entire codebase. Note that the fw.cfg file will stay pointing to the 3rdparty/amd_blobs/morgana/psp directory until the amd_blobs_repo is updated. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Ie9492a30ae9ff9cd7e15e0f2d239c32190ad4956 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71731 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-10soc/amd/common/fsp/Makefile: Fix an error messageAkihiko Odaki
It used to say "FSP-M binary larger than FSP_M_FILE", but FSP_M_FILE is the binary itself. The binary file size is actually compared with FSP_M_SIZE. Signed-off-by: Akihiko Odaki <akihiko.odaki@gmail.com> Change-Id: If58069944aea8e68117f2ee1d320726d8c6fdfc8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65440 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-09treewide: Remove unused <cpu/amd/msr.h>Elyes Haouas
Change-Id: Id24a7c7db24f49672df9d5ceefec5b7596f23e09 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-09soc/amd: Remove dummy SOC_SPECIFIC_OPTIONSElyes Haouas
Change-Id: I080b7b579338c3cf342beabda54f43f525d8b65c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-09soc/amd/morgana: Double max number of cpus for morganaRitul Guru
Change-Id: I5169a900345e2aabefcf1e2c249ee4bce6dc8fc5 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-09soc/amd/morgana: update morgana cpuidRitul Guru
Change-Id: Ieaad72a6b964f4b2ab572733694def88e30888a3 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-09soc/amd/mendocino/Kconfig: Remove TODO after reviewFred Reitberger
Remove TODO comments after reviewing against mendocino ppr #57243, rev 3.00 BUG=263563246 TEST=build skyrim Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ie56d481dd8b6b4e0a1e3d50f4ce75f50231fe4dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/71719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-09soc/amd/common/block/graphics: Fix whitespace consistencyFred Reitberger
Replace spaces with tabs for consistency. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I65b9bec7443094dfd2f6b0d6b11e0100023873b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-04soc/amd/mendocino: Hook up UPD dxio_tx_vboost_enable for PCIe optimizationChris.Wang
Add the UPD dxio_tx_vboost_enable for PCIe optimization. It will impact the PCIe signal integrity, need to double-confirm the SI result after enabling this setting. BUG=b:259622787 BRANCH=none TEST=confirm the setting has been set correspondingly with checking the FSP log. Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I05ae5b3091219e0cb1fe469c929fad6a725db678 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71562 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-03soc/amd/cezanne/psp_verstage/Makefile.inc: Remove path to non-existent ↵Elyes Haouas
directories Found using 'Wmissing-include-dirs' command option. Fix: cc1: error: ../../src/soc/amd/cezanne/psp_verstage/include: No such file or directory [-Werror=missing-include-dirs] Change-Id: I36022a031cc08d2af8b982522b3d6652e679bf14 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-03soc/amd/picasso/psp_verstage/Makefile.inc: Remove path to non-existent ↵Elyes Haouas
directories Found using 'Wmissing-include-dirs' command option. Fix: cc1: error: ../../src/soc/amd/picasso/psp_verstage/include: No such file or directory [-Werror=missing-include-dirs] Change-Id: I7713eef54686c58a83215c461c3274cec89e32b0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-03soc/amd/mendocino/psp_verstage/Makefile.inc: Remove path to non-existent ↵Elyes Haouas
directory Found using 'Wmissing-include-dirs' command option. Fix: cc1: error: ../../src/soc/amd/mendocino/psp_verstage/include: No such file or directory [-Werror=missing-include-dirs] Change-Id: I1cc084abc7a9bfed760350f304dd074081a7eebf Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-12-27tree/acpi: Replace constant "Zero" with actual numberFelix Singer
Change-Id: I5a3e3506415f424bf0fdd48fc449520a76622af5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71525 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27{acpi,arch,soc}/acpi: Replace constant "One" with actual numberFelix Singer
Change-Id: I3dfd7dd1de3bd27c35c195bd43c4a5b8c5a2dc53 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71522 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-24soc/amd/mendocino: Split the EFS from the AMDFW bodyKarthikeyan Ramasubramanian
Contents of unsigned AMDFW in RW sections are verified twice in PSP verstage - first time by vboot verifying the firmware body, second time by CBFS verification while the file is loaded to update PSP about the boot region. This redundant verification adds to boot time. Minimize the redundancy by splitting the EFS header from the AMDFW body and keep them as 2 separate CBFS files. This helps to improve the boot time by another 25 ms. BUG=None TEST=Build Skyrim BIOS image and boot to OS. Observe boot time improvement of ~25ms. Before: 6:end of verified boot 363,676 (16) 11:start of bootblock 641,392 (277,716) After: 6:end of verified boot 361,655 (16) 11:start of bootblock 616,967 (255,312) Change-Id: Ib18a4f5c6781e5a7868e9395c0f1212da0823100 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70839 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21soc/amd/common/psp_verstage: Report previous boot statusKarthikeyan Ramasubramanian
Add support to report previous PSP boot failure to verified boot. This is required specifically on mainboards where the signed AMDFW blobs are excluded from vboot verification. BUG=b:242825052 TEST=Build Skyrim BIOS image and boot to OS in Skyrim. Corrupt either one of SIGNED_AMDFW_A/B sections or both the sections to ensure that the appropriate FW slot is chosen. Cq-Depend: chromium:4064425 Change-Id: Iada0ec7c373db75765ba42cb531b16c2236b6cc3 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70382 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21vc/amd,soc/amd/mendocino: Add SVC_CMD_GET_PREV_BOOT_STATUSKarthikeyan Ramasubramanian
Add an SVC command to get the previous boot status. If there is any pre-x86 boot failure in the previous boot cycle, PSP stores it in warm reset persistent register and triggers a warm reset. PSP verstage on the subsequent boot gets the previous boot status and reports any failure to the vboot before a FW slot is selected. BUG=b:242825052 TEST=Build Skyrim BIOS image and boot to OS in Skyrim. Trigger a failure scenario by corrupting certain firmware blobs and observe that PSP reports the failure boot status. On a normal boot, observed that PSP reports successful boot. Change-Id: I440deee560b72c80491bfdd7fda38a1c3a4299e5 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70381 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-20soc/amd/mendocino: add dptc tablet mode supportChris.Wang
add dptc support for different power parameter on tablet/clamshell mode. BUG=b:257187831 BRANCH=none TEST=validate the parameter change for each mode by AGT. Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I96e04d113d18b42f3457056a5e4fa311ceccffb3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-12-20src/soc: Remove unneeded <assert.h>Elyes Haouas
As _Static_assert() is a compiler built-in, <assert.h> is not needed. Change-Id: I578b4bf286538d0606569d19ec760a1846c8145b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-16soc/amd/common/block/i2c: don't call die() when MMIO address is NULLFelix Held
There's no need to call die() in the case that the MMIO address of the I2C controller is NULL, so handle this case by returning a failure instead. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I12c143916ad551c56cc4ff75ae23754018817505 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14soc/amd/morgana/Kconfig: Remove TODO after reviewFred Reitberger
Remove more TODO comments after reviwing against morgana ppr #57396, rev 1.52 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I7fd9666a69d9a2b0902fa28ab0af0187198297ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/70466 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-14soc/amd/common/block/espi_util: drop unneeded check in espi_get_configFelix Held
Since soc_get_common_config will either return a valid pointer or cause a linking error, this function will also return a valid pointer or cause a linking error, so no need for additional runtime checks. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I99661247b9f8f47a708e3a6ff3f9e5359b505509 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70739 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-12-14soc/amd/*/config: drop invalid commentFelix Held
Since commit 28e61f16341f ("device: Use __pci_0_00_0_config in config_of_soc()") config_of_soc() was changed form being an actual function to a macro for the __pci_0_00_0_config struct pointer generated by util/sconfig. This change didn't only improve linker optimizations, but also turned runtime errors into link-time errors, so it's guaranteed that __pci_0_00_0_config won't be NULL and config_of_soc() won't "return" NULL. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id99ceaa9f7a70788da3f3068fb3da92d34fb6361 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70732 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-12-14soc/amd/common/block/espi_util: make espi_set_initial_config non-fatalFelix Held
Improve the espi_set_initial_config implementation so that a failure in there due to an invalid configuration won't call die() and stop booting at this point, but return an error to the caller so that the rest of the eSPI configuration will be skipped. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I97f730778a190c4485c4ffe93edf19bcbaa45392 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-12-14soc/amd/common/block/lpc/espi_util: make eSPI pin setup failure nonfatalFelix Held
Improve the eSPI pin configuration setup so that a failure in there won't call die() and stop booting at this point, but return an error to the caller so that the rest of the eSPI configuration will be skipped. This will prevent an early boot failure if the EC is missing or the eSPI interface is in a non-functional state. Also slightly shorten the function names so that the code still fits into 96 chars. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ice2d3a791d6a464eff4fb69d02aeca0bfe580be2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70730 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2022-12-13soc/amd/morgana: Enable GPP clk req disablingFred Reitberger
Enable GPP clk req disabling on morgana after reviewing against morgana ppr #57396, rev 1.52 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Id2502137486df7a8b0ac6a4b3e061b25b23e2e51 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70465 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-13soc/amd/morgana: Update pci int defsFred Reitberger
Update pci int defs per preview of next ppr after rev 1.52, #57396 Update birman and mayan mainboards to remove deleted PIRQs. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I10e13784761f0b9245f0ca10e3cd07d396ec4224 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70379 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12vc/amd/fsp/glinda/FspmUpd: don't use pointers for usb_phy configFelix Held
The size of a pointer changes between a 32 and 64 bit coreboot build. In order to be able to use a 32 bit FSP in a 64 bit coreboot build, change the pointer in the UPDs to a uint32_t to always have a 32 bit field in the UPD for this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5db2587ff74432a0ce1805d8d7ae76d650693eea Reviewed-on: https://review.coreboot.org/c/coreboot/+/70506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-12-12soc/amd/morgana: Remove emmc selectFred Reitberger
Morgana does not have emmc, so do not select it. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ib75618c137e825befc7384275f1a4ef9b5137b09 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70477 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12vc/amd/fsp/morgana/FspmUpd: don't use pointers for usb_phy configFelix Held
The size of a pointer changes between a 32 and 64 bit coreboot build. In order to be able to use a 32 bit FSP in a 64 bit coreboot build, change the pointer in the UPDs to a uint32_t to always have a 32 bit field in the UPD for this. Also make sure that the address of the lcl_usb_phy struct is located below the 4GB boundary, so that the truncation to 32 bits won't result in pointing to a different memory location than intended. In this error case, which I don't expect to happen, print an error and write 0 to mcfg->usb_phy_ptr so that the FSP will use its default values. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1394aa6ef5f401e0c7bdd4861f1e28ae46e56e4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/70505 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10treewide: Include <device/mmio.h> instead of <arch/mmio.h>Elyes Haouas
<device/mmio.h>` chain-include `<arch/mmio.h>: https://doc.coreboot.org/contributing/coding_style.html#headers-and-includes Also sort includes while on it. Change-Id: Ie62e4295ce735a6ca74fbe2499b41aab2e76d506 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-09soc/amd/mendocino: Enable LPC SPI DMAKarthikeyan Ramasubramanian
Enable LPC SPI DMA. This helps with ~20ms boot time improvement while loading various components synchronously. BUG=None TEST=Build Skyrim BIOS image and boot to OS. Observe a boot time improvement of ~20 ms. Before: Total Time: 1,503,032 After: Total Time: 1,485,536 Change-Id: I4dd57d46ae9bd664d57178d34b5beda872ed2cdb Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70383 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-08vc/amd/fsp/cezanne/FspmUpd: don't use pointers for usb_phy configurationFelix Held
The size of a pointer changes between a 32 and 64 bit coreboot build. In order to be able to use a 32 bit FSP in a 64 bit coreboot build, change the pointer in the UPDs to a uint32_t to always have a 32 bit field in the UPD for this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I81f3a38344f91cecb4fe5431ed211834e5ed599c Reviewed-on: https://review.coreboot.org/c/coreboot/+/69897 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-08vc/amd/fsp/mendocino/FspmUpd: don't use pointers for usb_phy configFelix Held
The size of a pointer changes between a 32 and 64 bit coreboot build. In order to be able to use a 32 bit FSP in a 64 bit coreboot build, change the pointer in the UPDs to a uint32_t to always have a 32 bit field in the UPD for this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I419fef73d2881e323487bc7fe641b2ac4041cb17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-12-08soc/amd/common/acpi, mb/google/skyrim: Implement DTTS ProposalEricKY Cheng
DTTS indicated Dynamic Thermal Table Switching.The proposal would like to develop the schematic for switching 6 thermal table by lid status, machine body mode and temperature. After entering the OS, the thermal table would be table A. If the “Motion” or “Lid status change” is detected. The thermal table would switch to laptop mode or lid close mode. Once the higher environment temperatures are detected,the thermal table would switch to the corresponding power throttle table (B, D or F). Based on these table switching mechanisms, no matter how the end-user uses Chromebook,they could enjoy more humanized thermal designs. Release Over Over Release . Temp. Temp. Temp. Temp. . -------------------------------------------------------- . Desktop mode Table A Table B 50C 45C . Lid open (Default) . -------------------------------------------------------- . Desktop mode Table C Table D 55C 50C . Lid close . -------------------------------------------------------- . Laptop mode Table E Table F 45C 40C . -------------------------------------------------------- . On the proposal, the transmission rules are list below: 1. Table A is the default table after booting. 2. A, C, E (Release Temp) can switch to each other. 3. B, D, F (Over Temp) can switch to each other. 4. A and B, C and D, E and F can switch to each other. 5. If Lid open/close or mode switch event trigger, temperature release tables will translation to each other, temperature over tables will translation to each other.After that event trigger, EC will check the new temperature condition and decide if the temperature need to be trigger.For example, if table A will switch to table D, table A will switch to C with Lid close event, if temperature is over 55C, EC will trigger temperature to switch form table C to D. 6. EC will trigger 3 times body-detection events during power on boot without any body-mode and lid status change. For this case if the previous table label is on same group, we will based on the temperature to decide the table. For example, assume table A is current table. When the temperature reaches 50C, than the table is switched from A to B. The current table is B. When the temperature is downgrade below 45C, the table is switched form B to A. The same rule is for C and D, E and F. BRANCH=none BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I866e5e497e2936984e713029b5f0b6d54cbc9622 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2022-12-08soc/amd/common/amdblocks/gpio: update amdblocks/gpio_defs.h includeFelix Held
Include <amdblocks/gpio_defs.h> instead of "gpio_defs.h", since gpio_defs.h is not only visible in a local scope, but also as <amdblocks/gpio_defs.h>. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iab3e5bb235a5b1bc995b6cf8710f0d8c1886142d Reviewed-on: https://review.coreboot.org/c/coreboot/+/70432 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-07soc/amd/common/block/acpi/ivrs: read IOAPIC IDs from hardwareFelix Held
TEST=IVRS table doesn't change on amd/mandolin Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5be04bc91425480992fcad12f8720738f9ca490e Reviewed-on: https://review.coreboot.org/c/coreboot/+/70357 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-06sb,soc/amd: Remove unused southbridge_io_trap_handler()Kyösti Mälkki
At the moment IO trap is not implemented for AMD platforms. Change-Id: Ib62ac4e4e418a8bab80c30dfb5183ecd8beb998d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-05soc/amd/common/block/include/gpio_defs.h: Fix documentationFred Reitberger
Fixing documentation of PAD_INT macro and replacing spaces with a tab to match the rest of the documentation. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I72a2578ce21dd10b3beb65c706440c3379f216d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70281 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-30soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal parametersEricKY Cheng
Expand DPTC_INPUT macro to supoort 13 DPTC thermal table parameters for dynamic table switching support. BRANCH=none BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I6d6a00f0eca0b0941860b9bc75da41d7a10d60e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-11-25ACPI: Use common code for MADT LAPIC NMIsKyösti Mälkki
Use the broadcast ID to deliver LINT1 as NMI to all CPUs, instead of listing individual LAPIC IDs. Change-Id: Iaf714d8c2aabd16c59c3bcebc4a207406fc85ca9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-24soc/amd: Define post codesMartin Roth
For the most part, this doesn't change any post codes, simply making the existing post-codes into macros. picasso/romstage.c did get a couple of post codes removed to match the other files. The POST_ROMSTAGE and POST_BOOTBLOCK codes are intended to become global at some point, while the POST_AGESA and POST_PSP codes would stay AMD specific. Change-Id: I007a09b6a3ed3280bac674cd74e298ec5c408ab7 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-23soc/amd/*/fsp_m_params: rework local USB PHY table updateFelix Held
Update the fields that need to be updated directly in the local static usb_phy_config struct instead of dereferencing the pointer written to the corresponding UPD field. This will allow updating the type of UPD field in a follow-up commit to enable 64 bit coreboot builds. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I44a9fe719e6803fc957fee3db13b261489ed313d Reviewed-on: https://review.coreboot.org/c/coreboot/+/69896 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-11-23soc/amd/*/Makefile: fix readelf parameters to get bootblock sizeFelix Held
This ports forward part of commit df0968062622 ("soc/amd/picasso: Add support for 64bit builds") to the newer AMD SoCs. Use -Wl instead of -l to get the output format that the commands in the Makefile expect to extract the value for PSP_BIOSBIN_SIZE. Without this change, readelf will split the output into two lines in case of a 64 bit coreboot build. This results in invalid amdcompress and amdfwtool command lines which will cause the amdfwtool call to fail with Error: BIOS binary destination and uncompressed size are required With the old readelf -l command we get this output in a 64 bit build: Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flags Align LOAD 0x0000000000000080 0x0000000002030000 0x0000000002030000 0x0000000000010000 0x0000000000010000 RWE 0x10 while we get the correct output in a 32 bit build: Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x000060 0x02030000 0x02030000 0x10000 0x10000 RWE 0x20 With readelf -Wl we also get the expected output in a 64 bit build: Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x000080 0x0000000002030000 0x0000000002030000 0x010000 0x010000 RWE 0x10 TEST=This fixes the 64 bit build on Cezanne with some follow-up patches applied. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I35f9feda4d0da3546592dfac233ca66732bd5464 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69895 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-11-21soc/amd/mendocino: Increase CBFS_MCACHE sizeKarthikeyan Ramasubramanian
CBFS_MCACHE is currently experiencing overflow with CBFS verification enabled. Reduce the pre-x86 cbmem console size from ~5.5 KiB to 4 KiB. This reduction along with the available free space in PSP shared buffer (32 KiB) helps to increase the CBFS_MCACHE size from 8 KiB to required 14 KiB. BUG=b:259342909 TEST=Build and boot to OS in Skyrim. Ensure that there are no CBFS mcache overflows. FMAP: area COREBOOT found @ 80a000 (8347648 bytes) VB2:vb2_digest_init() 0 bytes, hash algo 2, HW acceleration unsupported CBFS: mcache @0x00019a40 built for 67 files, used 0x19a0 of 0x1c00 bytes CBFS: Found 'apu/amdfw_a' @0x0 size 0x3ff80 in mcache @0x0001b640 VB2:vb2_digest_init() 262016 bytes, hash algo 2, HW acceleration enabled Ensure that firmware_CbfsMcache FAFT test is successful. Change-Id: I35e1a8c6d73e0870b6a43aac604f83a0b6c3aabe Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69827 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-18cbmem_top_chipset: Change the return value to uintptr_tElyes Haouas
Get rid of a lot of casts. Change-Id: I93645ef5dd270905ce421e68e342aff4c331eae6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2022-11-18soc/amd/acpi: Expand 5 DPTC thermal profiles acpigen support for AlibEricKY Cheng
Update acpigen_write_alib_dptc() to support extra 5 thermal profiles. User can use these profiles for dynamic thermal table switching support. BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I9e6d5c0fc6f492340c935899920d9ee7c9396256 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68470 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2022-11-17soc/amd: Use ioapic helper functionsKyösti Mälkki
Calling setup_ioapic() was only correct for the IOAPIC routing GSI 0..15 that mimic legacy PIC IRQs. Change-Id: Ifdacc61b72f461ec6bea334fa06651c09a9695d6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-17soc/amd/common/pi/def_callouts.c: Fix log messagesElyes Haouas
It is no longer necessary to explicitly add "Warning" in front of BIOS_WARNING message. Change-Id: If1645180dd98ff5a1661fd568554de5831ef237e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69623 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-16soc/amd/morgana/Kconfig: Remove TODO after reviewFred Reitberger
Remove TODO comments after reviwing against morgana ppr #57396, rev 1.52 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I598daf40a774ec81a956ce8c1aeb1cbbf4b475f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69275 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-16soc/amd/common: Don't set gcc specific options for clang buildsMartin Roth
Clang doesn't understand the -Wstack-usage=40960 option. Replace it with -Wframe-larger-than=40960. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I7d8b9c26d3fc861615a8553332ed1070974b751b Reviewed-on: https://review.coreboot.org/c/coreboot/+/69662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-16soc/amd/picasso: Add support for 64bit buildsArthur Heymans
Tested on google/vilboz (running the PCI rom with yabel). Change-Id: Icd72c4eef7805aacba6378632cbac7de9527673b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-11-15soc/amd: commonize generation of the PIC/APIC mapping tablesFelix Held
Now that we have a common init_tables in all mainboards using AMD SoCs, both the population of the fch_pic_routing and fch_apic_routing arrays and the definition of those arrays can be moved to the common AMD SoC code to not have the code duplicated in all mainboards. BUG=b:182782749 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: I8c65eca258272f0ef7dec3ece6236f5d00954c66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68853 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-14soc/amd/psp_smm_gen2.c: Fix 64bit mode integer conversionArthur Heymans
Explicitly cast integers to fix building for long mode. Change-Id: I9f56e183563c943d1c2bd0478c41a80512b47c5e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-14soc/amd/*/root_complex: use FSP HOB iterator functionsFelix Held
Use the newly added functions to iterate over the FSP HOBs to report the resources used by FSP to the resource allocator instead of open coding the iteration over the HOBs in the SoC code. TEST=Patch doesn't change reported resources on Mandolin Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I67ca346345c1fa08b008caa885d0a00d2d5afb12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-14arch/x86/Kconfig: Move AMD stages arch to common codeArthur Heymans
Use VBOOT_STARTS_BEFORE_BOOTBLOCK to determine whether the VERSTAGE needs to be build as x86 stage. Change-Id: I126801a1f6f523435935bb300f3e2807db347f63 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-13soc/amd/picasso: add mb_pre_fspm() definition and weak implementationMatt DeVillier
On newer AMD platforms, mb_pre_fspm() is used to set GPIOs in romstage for PCIe reset (currently set in bootblock) and touchscreen power sequencing (not yet implemented, but will be later in the patch train). Change-Id: Ia422aaa9e80355f9a9f8f850368441e5c8ff6598 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69452 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-12treewide: Replace ALIGN(x, a) by ALIGN_UP(x, a) for clarityElyes Haouas
Change-Id: I2a255cdcbcd38406f008a26fc0ed68d532e7a721 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-11soc/amd/root_complex: don't skip reporting IOAPIC resource in !hob caseFelix Held
When no HOB list is found, not only adding the resources reported by the FSP were skipped, but also adding the GNB IOAPIC resource was skipped. Fix this bug by moving the reporting of the GNB IOAPIC resource before the resources reported in the FSP HOBs to not skip the IOAPIC resource when there's no HOB list. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9174c8d7e5e94144187d27210e12f2dca3a6010f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69460 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-10/: Remove "ERROR: "/"WARNING: " prefixes from log messagesElyes Haouas
It is no longer necessary to explicitly add "ERROR: "/"WARNING: " in front of every BIOS_ERR/BIOS_WARN message. Change-Id: I22ee6ae15c3d3a848853c5460b3b3c1795adf2f5 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-09soc/amd/picasso/acpi: include pci_int_defs.asl from soc.aslFelix Held
Instead of including pci_int_defs.asl in each board's DSDT, include it in the common soc.asl. This moves the PRQM OperationRegion and the PRQI IndexField defined in pci_int_defs.asl into the \_SB scope, but those are defined inside the \_SB scope both in the Picasso reference code and for the AMD SoCs from Cezanne on. TEST=Both Linux and Windows still boot and don't show ACPI errors on Mandolin after moving this inside the \_SB scope Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib4e7bfb15de184cc43cd17c8249be0f59405793f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
2022-11-09soc/amd/picasso/acpi: rename pcie.asl to pci_int_defs.aslFelix Held
This aligns Picasso more with the newer AMD SoCs and also makes it a bit clearer what this file does. Also remove the unneeded tabs at the beginning of each line. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie6e5ee815e4346004bc864a6111a255dc689eae8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
2022-11-09soc/amd/common/block/spi: Mainboard to override SPI Read ModeKarthikeyan Ramasubramanian
On certain mainboards due to hardware design limitations, certain SPI Read Modes eg. (Dual I/O 1-2-2) cannot be supported. Add ability to override SPI read modes in boards which do not have hardware limitations. Currently there is an API to override SPI fast speeds. Update this API for mainboards to override SPI read mode as well. BUG=b:225213679 TEST=Build and boot to OS in Skyrim. Observe a boot time improvement of ~25 ms with 100 MHz SPI speeds. Before: 11:start of bootblock 688,046 14:finished loading romstage 30,865 16:FSP-M finished LZMA decompress (ignore for x86) 91,049 Total Time: 1,972,625 After: 11:start of bootblock 667,642 14:finished loading romstage 29,798 16:FSP-M finished LZMA decompress (ignore for x86) 87,743 Total Time: 1,943,924 Change-Id: I160b56f6201a798ce59e977ca40301e23ab63805 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-11-08vboot: Introduce handy vboot reboot functionsJakub Czapiga
This patch groups vboot context, recovery reason and subcode saving, and reboot calls into two handy functions: - vboot_save_and_reboot() - save context and reboot - vboot_fail_and_reboot() - store recovery reason and call function above Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ie29410e8985e7cf19bd8d4cccc393b050ca1f1c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69208 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-11-07soc/amd/mendocino: Enable x86 SHA acceleratorKarthikeyan Ramasubramanian
Enable x86 SHA accelerator for use by VBOOT library. This is useful when CBFS verification verifies the hash of the file being loaded in x86. BUG=b:227809919 TEST=Build and boot to OS in Skyrim. Observe a boot time improvement of ~10 ms with CBFS verification enabled. Change-Id: I14efe7be66f28f348330580d2e5733e11603a023 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68954 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-07soc/amd/common/include/gpio_defs.h: Add comment for accuracyFred Reitberger
The GPIO debounce timebase bit 4 is only 183uS on Picasso. On the other SoCs it is 244uS. This affects the 1mS and 2mS actual debounce times slightly. Time PCO Others 1mS 0.915mS 1.220mS 2mS 2.013mS 2.684mS Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Id84bef75e6ab134778721ca269d763a4bb2ddde5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69209 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-04src/soc/amd/mendocino: Enable override of MAINBOARD_BLOBS_DIRNikolai Vyssotski
When using site-local we need to have ability to override MAINBOARD_BLOBS_DIR with a different location (presumably somewhere in site-local). site-local Makefiles.inc should be pulled in first (different CL) allowing MAINBOARD_BLOBS_DIR to be overwritten. Change-Id: I028042b947887d1182642ad4482dd1bba7ad8e23 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-11-04soc/amd/*/data_fabric: Use common device opsFred Reitberger
Use the common device ops instead of an soc-specific device ops. TEST=builds for each soc Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I1804200c3c3f5ab492d237f4b03484c383862caf Reviewed-on: https://review.coreboot.org/c/coreboot/+/69174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-04soc/amd/common/data_fabric: Make common device opsFred Reitberger
Add the generic data_fabric_acpi_name function and device ops to common code. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I12053389a12081ddd81912a647bb532b31062093 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-04soc/amd/mendocino/data_fabric.c: Make function more genericFred Reitberger
Make the data_fabric_acpi_name function more generic, in preparation to move it to common. TEST=build chausie, dump ACPI tables, and inspect DFD0 to DFD7 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I77140d8d0d6bf3e048b737de03d18142a6e23c1d Reviewed-on: https://review.coreboot.org/c/coreboot/+/69172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-04soc/amd/*/data_fabric: Move register offsets to socFred Reitberger
Morgana/Glinda have a different register mapping for data fabric access, although the registers themselves are mostly compatible. The register layouts defined by each soc capture the differences and the common code can use those. Move the register offsets to soc headers and update the offsets for morgana/glinda per morgana ppr #57396, rev 1.52 and glinda ppr #57254, rev 1.51 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I9e5e7c85f99a9afa873764ade9734831fb5cfe69 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-04soc/amd/common/block/data_fabric: Use register bitslice structsFred Reitberger
Now that the socs have defined the DF FICAA and MMIO Control registers, update the common code to use them. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ia5566f7af6cf5444fc8c627e004dd08185468c77 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-04soc/amd: Specify memory types supported by each chipMartin Roth
This change disables support for memory types not used by each of the chips. This will in turn remove the files for those memory types from the platform builds. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I8c7f47b43d8d4a89630fbd645a725e61d74bc2a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-04soc/amd/common: Only call into enabled memory typesMartin Roth
Don't call into disabled memory type code, it won't work. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ie239039b3dd2b5d0a6f8e9230fd3466bb8309761 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03soc/amd/glinda/data_fabric: Add register bitslice structFred Reitberger
Add structs to define the data_fabric register bitfields, updated per glinda ppr #57254, rev 1.51 Update IOMS0_FABRIC_ID and DF_MMIO_NP per referenced ppr. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I509eaf5910d8d65ce0956200d7c00451ff9ce864 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03soc/amd/morgana/data_fabric: Add register bitslice structFred Reitberger
Add structs to define the data_fabric register bitfields, updated per morgana ppr #57396, rev 1.52 Update IOMS0_FABRIC_ID and DF_MMIO_NP per referenced ppr. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: If64c875026b643c584975f7abffad9b35f1a7b44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03soc/amd/mendocino/data_fabric: Add register bitslice structFred Reitberger
Add structs to define the data_fabric register bitfields. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I01dcea783542ecc0a761191907c1273016f854c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03soc/amd/picasso/data_fabric: Add register bitslice structFred Reitberger
Add structs to define the data_fabric register bitfields. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: If7cc94681cd5e282e09455c0ac7d3675884c3cf9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03soc/amd/cezanne/data_fabric: Add register bitslice structFred Reitberger
Add structs to define the data_fabric register bitfields. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ib5045812fb05eb8c3fb818d807e34decf69c6fff Reviewed-on: https://review.coreboot.org/c/coreboot/+/69068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03soc/amd/*/data_fabric: move data_fabric_set_mmio_np to commonFred Reitberger
The data_fabric_set_mmio_np function is effectively identical, so move it to common code. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I58e524a34a20e1c6f088feaf39d592b8d5efab58 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03soc/amd: Include <cpu/cpu.h> instead of <arch/cpu.h>Elyes Haouas
Also sort includes. Change-Id: Iea29938623fe1b2bcdd7f869b0accbc1f8758e7a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-31soc: Add SPDX license headers to MakefilesMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic875708697f07b6dae09d27dbd67eb8b960749f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-10-29soc/amd/common: Initialize STB Spill-to-DRAMMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I547671d2bcfe011566466665b14e151b8ec05430 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-10-29soc/amd/*/acpi/mmio.asl,sb_fch.asl: hide AAHB deviceFelix Held
Don't set bit 2 in _STA in order for Windows not to show a warning about an unknown device in the device manager for this device. Since the _STA object just returns a constant, a name definition can be used instead of a method definition. TEST=The unknown device with device instance path ACPI\AAHB0000\0 disappeared from the device manager in Windows 10 build 19045 on a Mandolin board with a Picasso APU. Just shutting down and then booting it again won't clear some internal state in Windows, so a reboot is needed instead for the change to become visible. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8cb1712756c3623cc3ea16210af69cde0fa18f62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-29soc/amd/glinda: Don't add amdfw.rom to cbfs in SOC MakefileMartin Roth
CB:66943 - commit 8d66fb1a705 (soc/amd: Add amdfw.rom in coreboot.pre) changed the build flow for the amd firmware binary after glinda was branched from morgana. Update glinda to match the other SoCs. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I5b0ccaa8c33e59f7146edd6a86f107480c152008 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>