diff options
| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2022-10-28 10:23:39 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-11-09 13:40:02 +0000 |
| commit | 5717ce6e995f7a442c2aec482091543391ef7784 (patch) | |
| tree | 0f558dc0266826f01c27a0ca847c6bc5161870e4 /src/soc/amd | |
| parent | d08deaabe15f39df6610df7bc06544722002279c (diff) | |
soc/amd/common/block/spi: Mainboard to override SPI Read Mode
On certain mainboards due to hardware design limitations, certain SPI
Read Modes eg. (Dual I/O 1-2-2) cannot be supported. Add ability to
override SPI read modes in boards which do not have hardware
limitations. Currently there is an API to override SPI fast speeds.
Update this API for mainboards to override SPI read mode as well.
BUG=b:225213679
TEST=Build and boot to OS in Skyrim. Observe a boot time improvement of
~25 ms with 100 MHz SPI speeds.
Before:
11:start of bootblock 688,046
14:finished loading romstage 30,865
16:FSP-M finished LZMA decompress (ignore for x86) 91,049
Total Time: 1,972,625
After:
11:start of bootblock 667,642
14:finished loading romstage 29,798
16:FSP-M finished LZMA decompress (ignore for x86) 87,743
Total Time: 1,943,924
Change-Id: I160b56f6201a798ce59e977ca40301e23ab63805
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/spi.h | 2 | ||||
| -rw-r--r-- | src/soc/amd/common/block/spi/fch_spi.c | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h index 4be3739bcf..dc7097f275 100644 --- a/src/soc/amd/common/block/include/amdblocks/spi.h +++ b/src/soc/amd/common/block/include/amdblocks/spi.h @@ -118,7 +118,7 @@ void spi_write16(uint8_t reg, uint16_t val); void spi_write32(uint8_t reg, uint32_t val); void fch_spi_config_modes(void); -void mainboard_spi_fast_speed_override(uint8_t *fast_speed); +void mainboard_spi_cfg_override(uint8_t *fast_speed, uint8_t *read_mode); /* Ensure you hold the mutex when performing SPI transactions */ extern struct thread_mutex spi_hw_mutex; diff --git a/src/soc/amd/common/block/spi/fch_spi.c b/src/soc/amd/common/block/spi/fch_spi.c index 5ef900c3c5..4a8482e97e 100644 --- a/src/soc/amd/common/block/spi/fch_spi.c +++ b/src/soc/amd/common/block/spi/fch_spi.c @@ -50,7 +50,7 @@ void show_spi_speeds_and_modes(void) printk(BIOS_DEBUG, "SPI Read Mode: %s\n", read_mode_str[DECODE_SPI_READ_MODE(val32)]); } -void __weak mainboard_spi_fast_speed_override(uint8_t *fast_speed) +void __weak mainboard_spi_cfg_override(uint8_t *fast_speed, uint8_t *read_mode) { /* No overriding SPI speeds. */ } @@ -107,7 +107,7 @@ void fch_spi_config_modes(void) read_mode = CONFIG_EFS_SPI_READ_MODE; fast_speed = CONFIG_EFS_SPI_SPEED; } - mainboard_spi_fast_speed_override(&fast_speed); + mainboard_spi_cfg_override(&fast_speed, &read_mode); if (fast_speed != CONFIG_EFS_SPI_SPEED) { normal_speed = lower_speed(normal_speed, fast_speed); |