tree/acpi: Replace constant "Zero" with actual number

Change-Id: I5a3e3506415f424bf0fdd48fc449520a76622af5
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71525
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

9 files changed, 38 insertions, 38 deletions

diff --git a/src/soc/amd/cezanne/acpi/pci0.asl b/src/soc/amd/cezanne/acpi/pci0.asl
index 7bd434a7f8..93bfb1fccd 100644
--- a/src/soc/amd/cezanne/acpi/pci0.asl
+++ b/src/soc/amd/cezanne/acpi/pci0.asl
@@ -6,7 +6,7 @@ Device(PCI0) {
 	External(TOM1, IntObj)		/* Generated by root_complex.c */
 
 	Method(_BBN, 0, NotSerialized) {
-		Return(Zero) /* Bus number = 0 */
+		Return(0) /* Bus number = 0 */
 	}
 
 	Method(_STA, 0, NotSerialized) {
diff --git a/src/soc/amd/common/acpi/dptc.asl b/src/soc/amd/common/acpi/dptc.asl
index aa70050ff3..84238d99a8 100644
--- a/src/soc/amd/common/acpi/dptc.asl
+++ b/src/soc/amd/common/acpi/dptc.asl
@@ -11,7 +11,7 @@ Scope (\_SB)
         /* If _SB.DDEF is not present, DPTC is not enabled so return early. */
         If (!CondRefOf (\_SB.DDEF))
         {
-            Return (Zero)
+            Return (0)
         }
 
         /* If _SB.DTHL is not present, then DPTC Tablet Mode is not enabled.
@@ -21,14 +21,14 @@ Scope (\_SB)
             (!\_SB.PCI0.LPCB.EC0.BTEX || \_SB.PCI0.LPCB.EC0.BFCR || \_SB.PCI0.LPCB.EC0.BFCT))
         {
             \_SB.DTHL()
-            Return (Zero)
+            Return (0)
         }
 
         /* If _SB.DTAB is not present, then DPTC Tablet Mode is not enabled. */
         If (CondRefOf (\_SB.DTAB) && (\_SB.PCI0.LPCB.EC0.TBMD == 1))
         {
             \_SB.DTAB()
-            Return (Zero)
+            Return (0)
         }
 
 #if CONFIG(FEATURE_DYNAMIC_DPTC)
@@ -36,6 +36,6 @@ Scope (\_SB)
 #else
         \_SB.DDEF()
 #endif
-        Return (Zero)
+        Return (0)
     }
 }
diff --git a/src/soc/amd/glinda/acpi/pci0.asl b/src/soc/amd/glinda/acpi/pci0.asl
index aa31c3302e..2f7e0baa06 100644
--- a/src/soc/amd/glinda/acpi/pci0.asl
+++ b/src/soc/amd/glinda/acpi/pci0.asl
@@ -8,7 +8,7 @@ Device(PCI0) {
 	External(TOM1, IntObj)		/* Generated by root_complex.c */
 
 	Method(_BBN, 0, NotSerialized) {
-		Return(Zero) /* Bus number = 0 */
+		Return(0) /* Bus number = 0 */
 	}
 
 	Method(_STA, 0, NotSerialized) {
diff --git a/src/soc/amd/mendocino/acpi/pci0.asl b/src/soc/amd/mendocino/acpi/pci0.asl
index e729ba38ff..5bf2f3e7c7 100644
--- a/src/soc/amd/mendocino/acpi/pci0.asl
+++ b/src/soc/amd/mendocino/acpi/pci0.asl
@@ -8,7 +8,7 @@ Device(PCI0) {
 	External(TOM1, IntObj)		/* Generated by root_complex.c */
 
 	Method(_BBN, 0, NotSerialized) {
-		Return(Zero) /* Bus number = 0 */
+		Return(0) /* Bus number = 0 */
 	}
 
 	Method(_STA, 0, NotSerialized) {
diff --git a/src/soc/amd/morgana/acpi/pci0.asl b/src/soc/amd/morgana/acpi/pci0.asl
index 7ccb00519f..3999d40c1c 100644
--- a/src/soc/amd/morgana/acpi/pci0.asl
+++ b/src/soc/amd/morgana/acpi/pci0.asl
@@ -8,7 +8,7 @@ Device(PCI0) {
 	External(TOM1, IntObj)		/* Generated by root_complex.c */
 
 	Method(_BBN, 0, NotSerialized) {
-		Return(Zero) /* Bus number = 0 */
+		Return(0) /* Bus number = 0 */
 	}
 
 	Method(_STA, 0, NotSerialized) {
diff --git a/src/soc/amd/picasso/acpi/northbridge.asl b/src/soc/amd/picasso/acpi/northbridge.asl
index f6e198f5f2..6850a1a0e4 100644
--- a/src/soc/amd/picasso/acpi/northbridge.asl
+++ b/src/soc/amd/picasso/acpi/northbridge.asl
@@ -10,7 +10,7 @@ Name(_CID, EISAID("PNP0A03"))	/* PCI Root Bridge */
 
 Method(_BBN, 0, NotSerialized)	/* Bus number = 0 */
 {
-	Return(Zero)
+	Return(0)
 }
 
 Method(_STA, 0, NotSerialized)
diff --git a/src/soc/amd/stoneyridge/acpi/northbridge.asl b/src/soc/amd/stoneyridge/acpi/northbridge.asl
index 042f66a4e1..7ed622541f 100644
--- a/src/soc/amd/stoneyridge/acpi/northbridge.asl
+++ b/src/soc/amd/stoneyridge/acpi/northbridge.asl
@@ -10,7 +10,7 @@ Name(_CID, EISAID("PNP0A03"))	/* PCI Root Bridge */
 
 Method(_BBN, 0, NotSerialized)	/* Bus number = 0 */
 {
-	Return(Zero)
+	Return(0)
 }
 
 Method(_STA, 0, NotSerialized)
diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
index d9556004c0..6a7ed2ea42 100644
--- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
+++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
@@ -410,7 +410,7 @@ Method(FDDC, 2, Serialized)
 		Switch(ToInteger(Arg0))
 		{
 			Case(5) {
-				I0PD = Zero
+				I0PD = 0
 				Local0 = I0DS
 				while(Local0 != 0x0) {
 					Local0 = I0DS
@@ -418,7 +418,7 @@ Method(FDDC, 2, Serialized)
 				I0TD = 0x03
 			}
 			Case(6) {
-				I1PD = Zero
+				I1PD = 0
 				Local0 = I1DS
 				while(Local0 != 0x0) {
 					Local0 = I1DS
@@ -426,7 +426,7 @@ Method(FDDC, 2, Serialized)
 				I1TD = 0x03
 			}
 			Case(7) {
-				I2PD = Zero
+				I2PD = 0
 				Local0 = I2DS
 				while(Local0 != 0x0) {
 					Local0 = I2DS
@@ -434,7 +434,7 @@ Method(FDDC, 2, Serialized)
 				I2TD = 0x03
 			}
 			Case(8) {
-				I3PD = Zero
+				I3PD = 0
 				Local0 = I3DS
 				while(Local0 != 0x0) {
 					Local0 = I3DS
@@ -442,7 +442,7 @@ Method(FDDC, 2, Serialized)
 				I3TD = 0x03
 			}
 			Case(11) {
-				U0PD = Zero
+				U0PD = 0
 				Local0 = U0DS
 				while(Local0 != 0x0) {
 					Local0 = U0DS
@@ -450,7 +450,7 @@ Method(FDDC, 2, Serialized)
 				U0TD = 0x03
 			}
 			Case(12) {
-				U1PD = Zero
+				U1PD = 0
 				Local0 = U1DS
 				while(Local0 != 0x0) {
 					Local0 = U1DS
@@ -461,7 +461,7 @@ Method(FDDC, 2, Serialized)
 			Case(18) { U2D3()} /* EHCI */
 			Case(23) { U3D3()} /* XHCI */
 			Case(24) { /* SD */
-				SDPD = Zero
+				SDPD = 0
 				Local0 = SDDS
 				while(Local0 != 0x0) {
 					Local0 = SDDS
@@ -472,7 +472,7 @@ Method(FDDC, 2, Serialized)
 		/* Turn off Power */
 		if (I0TD == 3) {
 			if (SATD == 3) {
-				if (SDTD == 3) { PG1A = Zero }
+				if (SDTD == 3) { PG1A = 0 }
 			}
 		}
 		if (I1TD == 3) {
@@ -481,7 +481,7 @@ Method(FDDC, 2, Serialized)
 					if (U0TD == 3) {
 						if (U1TD == 3) {
 							if (U2TD == 3) {
-								PG2_ = Zero
+								PG2_ = 0
 							}
 						}
 					}
diff --git a/src/soc/amd/stoneyridge/acpi/usb.asl b/src/soc/amd/stoneyridge/acpi/usb.asl
index 4d1aa7f33f..1626bb6f0c 100644
--- a/src/soc/amd/stoneyridge/acpi/usb.asl
+++ b/src/soc/amd/stoneyridge/acpi/usb.asl
@@ -5,7 +5,7 @@ Device(EHC0) {
 	Name(_ADR, 0x00120000)
 	Name(_PRW, Package() { 0xb, 3 })
 	Device (RHUB) {
-		Name (_ADR, Zero)
+		Name (_ADR, 0)
 		Device (HS01) { Name (_ADR, 1) }
 		Device (HS02) { Name (_ADR, 2) }
 		Device (HS03) { Name (_ADR, 3) }
@@ -121,14 +121,14 @@ Field(EHMC, DwordAcc, NoLock, Preserve)
 
 Method(U2D3,0, Serialized)
 {
-	if (EH10 != Zero) {
+	if (EH10 != 0) {
 		EHBA = EH10
 		EHME = 1
 		SSIM = ESIM
 	}
 
 	if (E_PS == 3) {
-		RQTY = Zero
+		RQTY = 0
 		RQ18 = 1
 
 		Local0 = U2SR
@@ -136,10 +136,10 @@ Method(U2D3,0, Serialized)
 			Local0 = U2SR
 		}
 
-		U2PD = Zero
+		U2PD = 0
 
 		Local0 = U2DS
-		while (Local0 != Zero) {
+		while (Local0 != 0) {
 			Local0 = U2DS
 		}
 
@@ -155,10 +155,10 @@ Method(U2D3,0, Serialized)
 Method(U2D0,0, Serialized)
 {
 	PWGC (0x40, 1)
-	U2RP = Zero
+	U2RP = 0
 	U2TD =  0x00
 
-	U2TD = Zero
+	U2TD = 0
 	U2PD = 1
 
 	Local0 = U2DS
@@ -175,7 +175,7 @@ Method(U2D0,0, Serialized)
 	EH2C = EHID
 
 
-	if (EH10 != Zero) {
+	if (EH10 != 0) {
 		EHBA = EH10
 		EHME = 1
 		ESIM = SSIM
@@ -196,7 +196,7 @@ Method(LXFW,3, Serialized)  //Load Xhci FirmWare
 	while (!Local0) {
 		Local0 = FPLC
 	}
-	FPLS = Zero
+	FPLS = 0
 }
 
 Method(U3D3,0, Serialized)
@@ -211,7 +211,7 @@ Method(U3D3,0, Serialized)
 		}
 		UD3P = 1 /* U3P_D3Cold_PWRDN */
 
-		U3PD = Zero /* PwrOnDev */
+		U3PD = 0 /* PwrOnDev */
 		Local0 = U3DS
 		while (Local0) { /* RstBState, RefClkOkState, PwrRstBState */
 			Local0 = U3DS
@@ -225,24 +225,24 @@ Method(U3D3,0, Serialized)
 			PGA3 &= 0x9f /* SwUsb2S5RstB */
 			U2RP = 1   /* USB2_RefClk_Pwdn */
 		}
-		U3PG = Zero /* XhcPwrGood  */
+		U3PG = 0 /* XhcPwrGood  */
 		U3PS = 1  /* Usb3PowerSel */
 	}
 }
 
 Method(U3D0,0, Serialized)
 {
-	U3PS = Zero /* Usb3PowerSel */
+	U3PS = 0 /* Usb3PowerSel */
 	U3PG = 1  /* XhcPwrGood  */
 
-	U2RP = Zero
-	U3RP = Zero
+	U2RP = 0
+	U3RP = 0
 
 	Local0 = PGA3 & 0xdf
 	Local0 |= 0x40
 	PGA3 = Local0 /* SwUsb2S5RstB */
 
-	U3TD = Zero /* TargetedDeviceState */
+	U3TD = 0 /* TargetedDeviceState */
 	U3PD = 1  /* PwrOnDev */
 
 	Local0 = U3DS /* wait for RstBState, RefClkOkState, PwrRstBState */
@@ -255,7 +255,7 @@ Method(U3D0,0, Serialized)
 		Local0 = U3PY
 	}
 
-	U3PR = Zero /* U3P_RESTORE_RESET */
+	U3PR = 0 /* U3P_RESTORE_RESET */
 
 	Local0 = AUSS /* AutoSizeStart */
 	if (Local0 != 1) {
@@ -272,7 +272,7 @@ Method(U3D0,0, Serialized)
 	X0_R ()
 
 	U3PR = 1  /* U3P_RESTORE_RESET */
-	UD3P = Zero /* U3P_D3Cold_PWRDN */
+	UD3P = 0 /* U3P_D3Cold_PWRDN */
 	U3TD = 1  /* TargetedDeviceState */
 }
 
@@ -314,7 +314,7 @@ CreateDWordField(SVBF, 0x7B0, SSIM) /* EHCI SIM BIT */
 Method(X0_S,0)
 {
 	XHID = XH2C
-	IDEX = Zero
+	IDEX = 0
 	S000 = DATA
 	IDEX = 0x00000004
 	S004 = DATA
@@ -375,7 +375,7 @@ Method(X0_S,0)
 Method(X0_R,0)
 {
 	XH2C = XHID
-	IDEX = Zero
+	IDEX = 0
 	DATA = S000
 	IDEX = 0x000000004
 	DATA = S004