coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2018-01-25	soc/amd/stoneyridge: Add I2C devicetree support.	Justin TerAvest
2018-01-25	src/amd/stoneyridge: Add devicetree ACPI names	Justin TerAvest
2017-12-22	soc/amd/stoneyridge/chip.c: Move setup_bsp_ramtop to soc_init()	Richard Spiegel
2017-12-15	soc/amd/common: Update agesawrapper_call.h	Richard Spiegel
2017-12-12	soc/amd/common: Move Agesa related headers	Richard Spiegel
2017-11-14	soc/amd/stoneyridge: Load SMU fimware using PSP	Marshall Dawson
2017-11-04	soc/amd/stoneyridge: remove superfluous NULL field initialization	Aaron Durbin
2017-09-27	amd/stoneyridge: Move AmdInitEnv to ramstage	Marshall Dawson
2017-09-27	amd/stoneyridge: Convert MP init to mp_init_with_smm	Marshall Dawson
2017-08-14	stoneyridge: Fix CPU ASL \_PR table	Marc Jones
2017-08-14	stoneyridge: Rename hudson to southbridge	Marc Jones
2017-06-27	soc/amd/stoneyridge: Fix most checkpatch errors	Marshall Dawson
2017-06-26	soc/amd/stoneyridge: Add northbridge support	Marc Jones
2017-06-26	soc: Add AMD Stoney Ridge southbridge code	Marc Jones